| /external/llvm/lib/Target/R600/ |
| AMDGPURegisterInfo.cpp | 1 //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
32 const uint16_t AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
54 case 0: return AMDGPU::sub0;
55 case 1: return AMDGPU::sub1;
56 case 2: return AMDGPU::sub2;
57 case 3: return AMDGPU::sub3;
58 case 4: return AMDGPU::sub4;
59 case 5: return AMDGPU::sub5;
60 case 6: return AMDGPU::sub6;
61 case 7: return AMDGPU::sub7
[all...] |
| SIInstrInfo.cpp | 43 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
46 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
47 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7
[all...] |
| R600RegisterInfo.cpp | 33 Reserved.set(AMDGPU::ZERO);
34 Reserved.set(AMDGPU::HALF);
35 Reserved.set(AMDGPU::ONE);
36 Reserved.set(AMDGPU::ONE_INT);
37 Reserved.set(AMDGPU::NEG_HALF);
38 Reserved.set(AMDGPU::NEG_ONE);
39 Reserved.set(AMDGPU::PV_X);
40 Reserved.set(AMDGPU::ALU_LITERAL_X);
41 Reserved.set(AMDGPU::ALU_CONST);
42 Reserved.set(AMDGPU::PREDICATE_BIT)
[all...] |
| R600ExpandSpecialInstrs.cpp | 17 #include "AMDGPU.h"
73 case AMDGPU::PRED_X: {
81 AMDGPU::ZERO); // src1
91 case AMDGPU::BREAK: {
93 AMDGPU::PRED_SETE_INT,
94 AMDGPU::PREDICATE_BIT,
95 AMDGPU::ZERO,
96 AMDGPU::ZERO);
101 TII->get(AMDGPU::PREDICATED_BREAK))
102 .addReg(AMDGPU::PREDICATE_BIT)
[all...] |
| SILowerControlFlow.cpp | 51 #include "AMDGPU.h"
139 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
141 .addReg(AMDGPU::EXEC);
156 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
158 .addReg(AMDGPU::EXEC);
161 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
167 .addReg(AMDGPU::VGPR0)
168 .addReg(AMDGPU::VGPR0)
169 .addReg(AMDGPU::VGPR0)
170 .addReg(AMDGPU::VGPR0)
[all...] |
| AMDGPUAsmPrinter.cpp | 1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===//
21 #include "AMDGPU.h"
87 if (reg == AMDGPU::VCC) {
93 case AMDGPU::EXEC:
94 case AMDGPU::M0:
98 if (AMDGPU::SReg_32RegClass.contains(reg)) {
101 } else if (AMDGPU::VReg_32RegClass.contains(reg)) {
104 } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
107 } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
110 } else if (AMDGPU::SReg_128RegClass.contains(reg))
[all...] |
| SIRegisterInfo.cpp | 36 case AMDGPU::GPRF32RegClassID:
37 return &AMDGPU::VReg_32RegClass;
46 case MVT::i32: return &AMDGPU::VReg_32RegClass;
|
| R600MachineScheduler.cpp | 146 if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
189 case AMDGPU::INTERP_PAIR_XY:
190 case AMDGPU::INTERP_PAIR_ZW:
191 case AMDGPU::INTERP_VEC_LOAD:
193 case AMDGPU::COPY:
216 case AMDGPU::sub0:
218 case AMDGPU::sub1:
220 case AMDGPU::sub2:
222 case AMDGPU::sub3:
230 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_XRegClass) |
[all...] |
| R600InstrInfo.cpp | 52 if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
53 && AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
56 buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
65 assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg)
66 && !AMDGPU::R600_Reg128RegClass.contains(SrcReg));
68 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
77 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
80 MIB.addReg(AMDGPU::ALU_LITERAL_X);
88 return AMDGPU::SETE_INT;
96 case AMDGPU::MOV
[all...] |
| Makefile | 12 TARGET = AMDGPU
|
| R600ISelLowering.cpp | 32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
34 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
35 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
109 case AMDGPU::CLAMP_R600: {
111 AMDGPU::MOV,
118 case AMDGPU::FABS_R600: {
120 AMDGPU::MOV,
127 case AMDGPU::FNEG_R600: {
129 AMDGPU::MOV
[all...] |
| SIISelLowering.cpp | 17 #include "AMDGPU.h"
35 addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass);
36 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
38 addRegisterClass(MVT::v16i8, &AMDGPU::SReg_128RegClass);
39 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
40 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
42 addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass);
43 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
45 addRegisterClass(MVT::v1i32, &AMDGPU::VReg_32RegClass);
47 addRegisterClass(MVT::v2i32, &AMDGPU::VReg_64RegClass)
[all...] |
| AMDGPUIndirectAddressing.cpp | 18 #include "AMDGPU.h"
102 if (MI.getOperand(1).getReg() == AMDGPU::INDIRECT_BASE_ADDR) {
106 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::COPY), DstReg)
189 TII->get(AMDGPU::PHI), PhiDstReg);
214 if (MI.getOpcode() == AMDGPU::PHI) {
250 if (MI.getOperand(1).getReg() == AMDGPU::INDIRECT_BASE_ADDR) {
261 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::COPY),
268 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::COPY),
281 TII->get(AMDGPU::REG_SEQUENCE),
326 if (DefInstr->getOpcode() == AMDGPU::PHI)
[all...] |
| AMDGPUInstrInfo.h | 1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
28 #define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT
29 #define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT
30 #define OPCODE_IS_ZERO AMDGPU::PRED_SETE
31 #define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE
|
| AMDGPUInstrInfo.cpp | 92 case AMDGPU::BRANCH_COND_i32:
93 case AMDGPU::BRANCH_COND_f32:
94 case AMDGPU::BRANCH:
108 if (tmp->getOpcode() == AMDGPU::ENDLOOP
109 || tmp->getOpcode() == AMDGPU::ENDIF
110 || tmp->getOpcode() == AMDGPU::ELSE) {
|
| SIInsertWaits.cpp | 19 #include "AMDGPU.h"
131 (MI.getOpcode() == AMDGPU::EXP || MI.getDesc().mayStore()));
162 if (MI.getOpcode() == AMDGPU::EXP)
213 ExpInstrTypesSeen |= MI.getOpcode() == AMDGPU::EXP ? 1 : 2;
241 if (I != MBB.end() && I->getOpcode() == AMDGPU::S_ENDPGM)
290 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
|
| AMDILISelDAGToDAG.cpp | 11 /// \brief Defines an instruction selector for the AMDGPU target.
35 /// AMDGPU specific code to select AMDGPU machine instructions for
38 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
85 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
175 CurDAG->getTargetConstant(AMDGPU::R600_Reg128RegClassID, MVT::i32),
176 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
177 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32),
178 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub2, MVT::i32),
179 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub3, MVT::i32
[all...] |
| SIInstrInfo.h | 76 namespace AMDGPU {
80 } // End namespace AMDGPU
|
| AMDILCFGStructurizer.cpp | [all...] |
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 147 } else if (MI.getOpcode() == AMDGPU::RETURN ||
148 MI.getOpcode() == AMDGPU::BUNDLE ||
149 MI.getOpcode() == AMDGPU::KILL) {
153 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
154 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
160 case AMDGPU::CONSTANT_LOAD_eg:
161 case AMDGPU::VTX_READ_PARAM_8_eg:
162 case AMDGPU::VTX_READ_PARAM_16_eg:
163 case AMDGPU::VTX_READ_PARAM_32_eg:
164 case AMDGPU::VTX_READ_PARAM_128_eg
[all...] |
| SIMCCodeEmitter.cpp | 80 return (AMDGPU::SSrc_32RegClassID == RegClass) ||
81 (AMDGPU::SSrc_64RegClassID == RegClass) ||
82 (AMDGPU::VSrc_32RegClassID == RegClass) ||
83 (AMDGPU::VSrc_64RegClassID == RegClass);
|
| AMDGPUMCTargetDesc.cpp | 1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
11 /// \brief This file provides AMDGPU specific target descriptions.
78 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
|
| /external/llvm/lib/Target/R600/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
32 case AMDGPU::PRED_SEL_OFF: break;
|
