| /external/v8/src/mips/ |
| constants-mips.cc | 315 case ANDI:
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| constants-mips.h | 267 ANDI = ((1 << 3) + 4) << kOpcodeShift,
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| assembler-mips.cc | 650 return GetOpcodeField(instr) == ANDI;
1246 void Assembler::andi(Register rt, Register rs, int32_t j) { function in class:v8::Assembler
[all...] |
| simulator-mips.cc | [all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.h | 305 void ANDI(int Rd, int Rs, uint16_t imm);
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| MIPSAssembler.cpp | 437 mMips->ANDI(Rd, Rn, src);
[all...] |
| /external/qemu/tcg/ppc/ |
| tcg-target.c | 321 #define ANDI OPCD(28)
[all...] |
| /external/qemu/tcg/ppc64/ |
| tcg-target.c | 309 #define ANDI OPCD( 28)
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| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 49 MBlaze::ORI, MBlaze::ANDI, MBlaze::XORI, MBlaze::ANDNI, //28,29,2A,2B
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| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 264 // andi samt, samt, 31
297 BuildMI(MBB, dl, TII->get(MBlaze::ANDI), IAMT)
444 // andi samt, samt, 31
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| /external/valgrind/main/none/tests/mips32/ |
| MIPS32int.stdout.exp | 81 ANDI
82 andi $t0, $t1, 1 :: rt 0x00000000 rs 0x00000000, imm 0x00000001
83 andi $t0, $t1, 0 :: rt 0x00000000 rs 0x00000001, imm 0x00000000
84 andi $t0, $t1, 1 :: rt 0x00000001 rs 0x00000001, imm 0x00000001
85 andi $t0, $t1, 1 :: rt 0x00000001 rs 0x7fffffff, imm 0x00000000
86 andi $t0, $t1, 0 :: rt 0x00000000 rs 0x80000000, imm 0x00000000
87 andi $t0, $t1, 0x3145 :: rt 0x00003145 rs 0xffffffff, imm 0x00003145
[all...] |
