| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypesGeneric.cpp | 54 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
55 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
61 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
62 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
68 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
69 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
74 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
75 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
78 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST");
88 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo)
[all...] |
| LegalizeVectorOps.cpp | 328 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
335 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
616 // Bitcast the operands to be the same type as the mask.
619 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
620 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
629 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
678 // Bitcast the operands to be the same type as the mask.
681 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
682 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
691 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val)
[all...] |
| LegalizeVectorTypes.cpp | 50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
151 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
365 case ISD::BITCAST:
404 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
500 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
640 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
641 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
649 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
650 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
664 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo)
[all...] |
| SelectionDAGBuilder.cpp | 134 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
135 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
167 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
168 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
210 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
286 // Vector/Vector bitcast.
288 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
299 // Trivial bitcast if the types are the same size and the destination
303 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
375 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val)
[all...] |
| LegalizeDAG.cpp | 318 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
441 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
740 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
[all...] |
| LegalizeFloatTypes.cpp | 61 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break;
609 case ISD::BITCAST: Res = SoftenFloatOp_BITCAST(N); break;
636 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0),
[all...] |
| FastISel.cpp | 137 !(I->getOpcode() == Instruction::BitCast ||
758 // If the bitcast doesn't change the type, just use the operand value.
767 // Bitcasts of other values become reg-reg copies or BITCAST operators.
784 // First, try to perform the bitcast by inserting a reg-reg copy.
797 // If the reg-reg copy failed, select a BITCAST opcode.
799 ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
898 // Bitcast the value to integer, twiddle the sign bit with xor,
899 // and then bitcast it back to floating-point.
906 ISD::BITCAST, OpReg, OpRegIsKill);
[all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAGDumper.cpp | 229 case ISD::BITCAST: return "bitcast";
|
| LegalizeTypes.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
220 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
235 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
254 // make us bitcast between two vectors which are legalized in different ways.
256 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
769 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
[all...] |
| SelectionDAG.cpp | 100 if (N->getOpcode() == ISD::BITCAST)
148 if (N->getOpcode() == ISD::BITCAST)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 425 /// BITCAST - This operator converts between integer, vector and FP
432 BITCAST,
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 342 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
343 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
345 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
347 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
[all...] |
| X86FastISel.cpp | 365 case Instruction::BitCast:
613 case Instruction::BitCast:
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 204 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
212 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
259 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
431 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
521 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
729 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
730 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 47 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
|
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 580 // Bitcast True / False to the correct types. This will end up being
584 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
585 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
613 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
[all...] |
| AMDILISelDAGToDAG.cpp | 408 case ISD::BITCAST:
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 201 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
202 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
203 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
204 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 127 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
128 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
