| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 500 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
504 BR_CC,
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 58 BR_CC,
|
| MSP430ISelLowering.cpp | 109 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
110 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
196 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
790 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 33 BR_CC,
76 /// BR_CC instructions. Second, it gives a legal instruction for the actual
|
| AArch64ISelLowering.cpp | 91 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
92 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
93 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
94 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
227 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
767 case AArch64ISD::BR_CC: return "AArch64ISD::BR_CC";
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 104 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
105 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
106 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
107 setOperationAction(ISD::BR_CC, MVT::i8, Expand);
108 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
109 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
110 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 740 // Sparc doesn't have BRCOND either, it has BR_CC.
744 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
745 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
746 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 253 case ISD::BR_CC: return "br_cc";
|
| LegalizeDAG.cpp | [all...] |
| LegalizeFloatTypes.cpp | 610 case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break;
[all...] |
| LegalizeIntegerTypes.cpp | 770 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
[all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 163 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
164 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 53 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
54 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 280 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
281 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
282 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
283 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| PPCISelLowering.cpp | 470 setTargetDAGCombine(ISD::BR_CC);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 379 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
380 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
381 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
382 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
383 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
384 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
385 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 87 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
