| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 712 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
714 CCInfo.AnalyzeCallOperands(Outs, CC_MBlaze);
717 unsigned NumBytes = CCInfo.getNextStackOffset();
851 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
854 CCInfo.AnalyzeCallResult(Ins, RetCC_MBlaze);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 324 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
326 CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
330 unsigned Offset = CCInfo.getNextStackOffset();
420 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
424 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
470 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
473 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
476 unsigned NumBytes = CCInfo.getNextStackOffset();
607 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
610 CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 92 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
96 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
159 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
161 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
304 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6);
306 unsigned ArgOffset = CCInfo.getNextStackOffset();
363 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
365 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
368 unsigned ArgsSize = CCInfo.getNextStackOffset();
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 823 AArch64TargetLowering::SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG,
832 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(AArch64ArgRegs,
834 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(AArch64FPRArgRegs,
[all...] |
| AArch64ISelLowering.h | 146 void SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG,
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| MipsISelLowering.h | 239 const CCState &getCCInfo() const { return CCInfo; }
292 CCState &CCInfo;
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 476 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
484 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
|
| ARMFastISel.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 311 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
315 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
362 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
365 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
399 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
421 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
423 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
448 unsigned NumBytes = CCInfo.getNextStackOffset();
828 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
831 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon)
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 140 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
146 CCInfo.AllocateReg(AMDGPU::VGPR0);
147 CCInfo.AllocateReg(AMDGPU::VGPR1);
150 AnalyzeFormalArguments(CCInfo, Splits);
|
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 751 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,
753 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | [all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | [all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_3_0/ |
| BitcodeReader.cpp | [all...] |
