/external/llvm/lib/Target/ARM/ |
Thumb2RegisterInfo.h | 36 ARMCC::CondCodes Pred = ARMCC::AL,
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Thumb2ITBlockPass.cpp | 43 ARMCC::CondCodes CC, ARMCC::CondCodes OCC, 105 ARMCC::CondCodes CC, ARMCC::CondCodes OCC, 153 ARMCC::CondCodes NCC = getITInstrPredicate(I, NPredReg); 170 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); 193 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); 206 ARMCC::CondCodes NCC = getITInstrPredicate(NMI, NPredReg);
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Thumb1RegisterInfo.h | 42 ARMCC::CondCodes Pred = ARMCC::AL,
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Thumb2InstrInfo.h | 70 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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Thumb2RegisterInfo.cpp | 40 ARMCC::CondCodes Pred, unsigned PredReg,
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ARMBaseInstrInfo.h | 77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const { 79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm() 364 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 385 ARMCC::CondCodes Pred, unsigned PredReg, 391 ARMCC::CondCodes Pred, unsigned PredReg,
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ARMBaseRegisterInfo.h | 158 ARMCC::CondCodes Pred = ARMCC::AL,
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ARMLoadStoreOptimizer.cpp | 95 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, 108 ARMCC::CondCodes Pred, 115 ARMCC::CondCodes Pred, unsigned PredReg, 285 int Opcode, ARMCC::CondCodes Pred, 371 ARMCC::CondCodes Pred, unsigned PredReg, 448 ARMCC::CondCodes Pred, unsigned PredReg, 531 ARMCC::CondCodes Pred, unsigned PredReg) { 564 ARMCC::CondCodes Pred, unsigned PredReg) { 719 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 872 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg) [all...] |
ARMBaseInstrInfo.cpp | 162 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 440 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 489 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 490 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); [all...] |
ARMBaseRegisterInfo.cpp | 369 ARMCC::CondCodes Pred, 721 ARMCC::CondCodes Pred = (PIdx == -1) 722 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
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Thumb2InstrInfo.cpp | 61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); 180 ARMCC::CondCodes Pred, unsigned PredReg, 566 ARMCC::CondCodes
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ARMISelLowering.h | 545 ARMCC::CondCodes CC = ARMCC::AL) const; 550 ARMCC::CondCodes Cond) const;
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MLxExpansionPass.cpp | 283 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm();
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Thumb2SizeReduction.cpp | 156 bool is2Addr, ARMCC::CondCodes Pred, 265 bool is2Addr, ARMCC::CondCodes Pred, 661 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 759 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430.h | 23 enum CondCodes {
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MSP430InstrInfo.cpp | 130 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); 225 MSP430CC::CondCodes BranchCode = 226 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm()); 248 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
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/external/llvm/lib/Target/NVPTX/ |
NVPTX.h | 32 enum CondCodes { 42 inline static const char *NVPTXCondCodeToString(NVPTXCC::CondCodes CC) {
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/external/llvm/lib/Target/Sparc/ |
Sparc.h | 37 enum CondCodes { 74 inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) {
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SparcInstrInfo.cpp | 79 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) 181 SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
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SparcAsmPrinter.cpp | 177 O << SPARCCondCodeToString((SPCC::CondCodes)CC);
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMBaseInfo.h | 27 // The CondCodes constants map directly to the 4-bit encoding of the 29 enum CondCodes { // Meaning (integer) Meaning (floating-point) 47 inline static CondCodes getOppositeCondition(CondCodes CC) { 68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
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/external/llvm/lib/Target/AArch64/Utils/ |
AArch64BaseInfo.h | 28 // The CondCodes constants map directly to the 4-bit encoding of the 30 enum CondCodes { // Meaning (integer) Meaning (floating-point) 54 inline static const char *A64CondCodeToString(A64CC::CondCodes CC) { 76 inline static A64CC::CondCodes A64StringToCondCode(StringRef CondStr) { 77 return StringSwitch<A64CC::CondCodes>(CondStr.lower()) 100 inline static A64CC::CondCodes A64InvertCondCode(A64CC::CondCodes CC) { 104 return static_cast<A64CC::CondCodes>(static_cast<unsigned>(CC) ^ 0x1);
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/external/llvm/lib/Target/AArch64/ |
AArch64BranchFixupPass.cpp | 494 A64CC::CondCodes CC = (A64CC::CondCodes)MI->getOperand(0).getImm();
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AArch64ISelLowering.h | 191 A64CC::CondCodes Cond) const;
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AArch64ISelLowering.cpp | 389 A64CC::CondCodes Cond) const { [all...] |