| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCInst.h | 24 // MCID is set during instruction lowering.
27 const MCInstrDesc *MCID;
34 MCInst(), MCID(0), packetStart(0), packetEnd(0) {};
35 HexagonMCInst(const MCInstrDesc& mcid):
36 MCInst(), MCID(&mcid), packetStart(0), packetEnd(0) {};
50 void setDesc(const MCInstrDesc& mcid) { MCID = &mcid; };
51 const MCInstrDesc& getDesc(void) const { return *MCID; };
[all...] |
| HexagonMCInst.cpp | 33 const uint64_t F = MCID->TSFlags;
40 return (!MCID->isPseudo() &&
52 const uint64_t F = MCID->TSFlags;
58 const uint64_t F = MCID->TSFlags;
64 const uint64_t F = MCID->TSFlags;
70 const uint64_t F = MCID->TSFlags;
118 const uint64_t F = MCID->TSFlags;
124 const uint64_t F = MCID->TSFlags;
130 const uint64_t F = MCID->TSFlags;
136 const uint64_t F = MCID->TSFlags
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 98 namespace MCID {
191 return Flags & (1 << MCID::Variadic);
197 return Flags & (1 << MCID::HasOptionalDef);
204 return Flags & (1 << MCID::Pseudo);
209 return Flags & (1 << MCID::Return);
214 return Flags & (1 << MCID::Call);
221 return Flags & (1 << MCID::Barrier);
231 return Flags & (1 << MCID::Terminator);
239 return Flags & (1 << MCID::Branch);
245 return Flags & (1 << MCID::IndirectBranch)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc();
23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
26 unsigned Opcode = MCID.getOpcode();
43 const MCInstrDesc &MCID = MI->getDesc();
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
|
| ARMCodeEmitter.cpp | 101 const MCInstrDesc &MCID,
107 const MCInstrDesc &MCID) const;
279 const MCInstrDesc &MCID = MI.getDesc();
282 unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ?
485 const MCInstrDesc &MCID = MI.getDesc();
487 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
821 const MCInstrDesc &MCID = MI.getDesc();
829 Binary |= getAddrModeSBit(MI, MCID);
848 const MCInstrDesc &MCID = MI.getDesc();
857 Binary |= getAddrModeSBit(MI, MCID);
[all...] |
| Thumb2SizeReduction.cpp | 203 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) {
204 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
523 const MCInstrDesc &MCID = MI->getDesc();
524 if (MCID.hasOptionalDef() &&
525 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
673 const MCInstrDesc &MCID = MI->getDesc();
674 if (MCID.hasOptionalDef()) {
675 unsigned NumOps = MCID.getNumOperands();
701 unsigned NumOps = MCID.getNumOperands();
703 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()
[all...] |
| MLxExpansionPass.cpp | 186 const MCInstrDesc &MCID = MI->getDesc();
187 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
190 unsigned Opcode = MCID.getOpcode();
343 const MCInstrDesc &MCID = MI->getDesc();
351 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
361 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
|
| Thumb2ITBlockPass.cpp | 140 const MCInstrDesc &MCID = MI->getDesc();
142 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
|
| Thumb1RegisterInfo.cpp | 241 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
243 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)
291 const MCInstrDesc &MCID = TII.get(ExtraOpc);
292 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
319 const MCInstrDesc &MCID = TII.get(ARM::tRSB);
320 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
|
| ARMBaseRegisterInfo.cpp | 553 const MCInstrDesc &MCID = TII.get(ADDriOpc);
556 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
558 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 70 const MCInstrDesc *MCID; // Instruction descriptor.
112 MachineInstr(MachineFunction&, const MCInstrDesc &MCID,
257 const MCInstrDesc &getDesc() const { return *MCID; }
261 int getOpcode() const { return MCID->Opcode; }
329 return hasProperty(MCID::Variadic, Type);
335 return hasProperty(MCID::HasOptionalDef, Type);
342 return hasProperty(MCID::Pseudo, Type);
346 return hasProperty(MCID::Return, Type);
350 return hasProperty(MCID::Call, Type);
357 return hasProperty(MCID::Barrier, Type)
[all...] |
| MachineInstrBuilder.h | 225 const MCInstrDesc &MCID) {
226 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL));
234 const MCInstrDesc &MCID,
236 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL))
247 const MCInstrDesc &MCID,
250 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
258 const MCInstrDesc &MCID,
261 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
269 const MCInstrDesc &MCID,
273 return BuildMI(BB, MII, DL, MCID, DestReg)
[all...] |
| /external/llvm/lib/CodeGen/ |
| ScoreboardHazardRecognizer.cpp | 128 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
129 if (MCID == NULL) {
133 unsigned idx = MCID->getSchedClass();
184 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
185 assert(MCID && "The scheduler must filter non-machineinstrs");
186 if (DAG->TII->isZeroCost(MCID->Opcode))
193 unsigned idx = MCID->getSchedClass();
|
| TargetInstrInfo.cpp | 39 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
42 if (OpNum >= MCID.getNumOperands())
45 short RegClass = MCID.OpInfo[OpNum].RegClass;
46 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
120 const MCInstrDesc &MCID = MI->getDesc();
121 bool HasDef = MCID.getNumDefs();
185 const MCInstrDesc &MCID = MI->getDesc();
186 if (!MCID.isCommutable())
190 SrcOpIdx1 = MCID.getNumDefs();
220 const MCInstrDesc &MCID = MI->getDesc()
[all...] |
| MachineInstr.cpp | 521 if (MCID->ImplicitDefs)
522 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
524 if (MCID->ImplicitUses)
525 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
534 : MCID(&tid), Parent(0), Operands(0), NumOperands(0),
538 if (unsigned NumOps = MCID->getNumOperands() +
539 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
551 : MCID(&MI.getDesc()), Parent(0), Operands(0), NumOperands(0),
623 assert(MCID && "Cannot add operands before providing an instr descriptor")
[all...] |
| MachineVerifier.cpp | 760 const MCInstrDesc &MCID = MI->getDesc();
761 if (MI->getNumOperands() < MCID.getNumOperands()) {
763 *OS << MCID.getNumOperands() << " operands expected, but "
804 const MCInstrDesc &MCID = MI->getDesc();
806 // The first MCID.NumDefs operands must be explicit register defines
807 if (MONum < MCID.getNumDefs()) {
808 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
815 } else if (MONum < MCID.getNumOperands()) {
816 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
820 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1))
[all...] |
| PeepholeOptimizer.cpp | 421 const MCInstrDesc &MCID = MI->getDesc();
422 if (MCID.getNumDefs() != 1)
441 const MCInstrDesc &MCID = MI->getDesc();
444 if (MCID.getNumDefs() != 1)
|
| RegAllocFast.cpp | 805 const MCInstrDesc &MCID = MI->getDesc();
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
28 if (!MCID)
94 const MCInstrDesc &MCID = TII.get(Opcode);
96 isLoad = MCID.mayLoad();
97 isStore = MCID.mayStore();
99 uint64_t TSFlags = MCID.TSFlags;
|
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 152 const MCInstrDesc &MCID = MI->getDesc();
154 if (MCID.mayLoad())
156 if (MCID.mayStore())
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGFast.cpp | 257 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
258 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
259 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
264 if (MCID.isCommutable())
435 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
436 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
437 unsigned NumRes = MCID.getNumDefs();
438 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
513 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
514 if (!MCID.ImplicitDefs
[all...] |
| InstrEmitter.cpp | 308 const MCInstrDesc &MCID = MIB->getDesc();
309 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
310 MCID.OpInfo[IIOpNum].isOptionalDef();
345 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
[all...] |
| ScheduleDAGSDNodes.cpp | 299 const MCInstrDesc &MCID = TII->get(Opc);
300 if (MCID.mayLoad())
434 const MCInstrDesc &MCID = TII->get(Opc);
435 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
436 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
441 if (MCID.isCommutable())
[all...] |
| ScheduleDAGRRList.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 108 const MCInstrDesc &MCID = get(Opc);
109 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
|
