| /external/clang/test/SemaTemplate/ |
| nested-name-spec-template.cpp | 5 template<typename T> struct Promote;
7 template<> struct Promote<short> {
11 template<> struct Promote<int> {
15 template<> struct Promote<float> {
19 Promote<short>::type *ret_intptr(int* ip) { return ip; }
20 Promote<int>::type *ret_intptr2(int* ip) { return ip; }
23 M::Promote<int>::type *ret_intptr3(int* ip) { return ip; }
24 M::template Promote<int>::type *ret_intptr4(int* ip) { return ip; } // expected-warning{{'template' keyword outside of a template}}
25 M::template Promote<int> pi; // expected-warning{{'template' keyword outside of a template}}
28 N::M::Promote<int>::type *ret_intptr5(int* ip) { return ip;
[all...] |
| /external/llvm/examples/OCaml-Kaleidoscope/Chapter7/ |
| toy.ml | 33 (* Promote allocas to registers. *)
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 51 setOperationAction(ISD::STORE, MVT::f32, Promote);
54 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
57 setOperationAction(ISD::LOAD, MVT::f32, Promote);
60 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 462 // Promote the value if needed.
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 82 Promote, // This operation should be executed in a larger type.
287 /// it is already legal (return 'Legal') or we need to promote it to a larger
288 /// type (return 'Promote'), or we need to expand it into multiple registers
299 /// returns the larger type to promote to. For integer types that are larger
418 getOperationAction(Op, VT) == Promote);
523 assert(Action != Promote && "Can't promote condition code!");
536 /// getTypeToPromoteTo - If the action for this operation is to promote, this
537 /// method returns the ValueType to promote to.
539 assert(getOperationAction(Op, VT) == Promote &
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 93 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
94 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
95 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
733 // Promote the value if needed.
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 237 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
255 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
257 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
258 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
259 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
262 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
273 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
275 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
276 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 86 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
88 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
491 // Promote the value if needed.
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 91 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
240 // VAARG always uses double-word chunks, so promote anything smaller.
241 setOperationAction(ISD::VAARG, MVT::i1, Promote);
243 setOperationAction(ISD::VAARG, MVT::i8, Promote);
245 setOperationAction(ISD::VAARG, MVT::i16, Promote);
247 setOperationAction(ISD::VAARG, MVT::i32, Promote);
290 // We cannot do this with Promote because i64 is not a legal type.
329 // We promote all shuffles to v16i8.
330 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
333 // We promote all non-typed operations to v4i32
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 130 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
131 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
132 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 261 case TargetLowering::Promote:
264 // "Promote" the operation by bitcasting
270 // "Promote" the operation by extending the operand.
321 "Can't promote a vector with multiple results!");
343 "Can't promote a vector with multiple results!");
345 // Normal getTypeToPromoteTo() doesn't work here, as that will promote
|
| LegalizeDAG.cpp | 191 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
736 case TargetLowering::Promote: {
739 "Can only promote stores to same size type");
758 // Promote to a byte-sized store with upper bits zero if no
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 163 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
164 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 76 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
77 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
78 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 211 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
212 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
213 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 417 // Promote the value if needed.
701 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 96 setOperationAction(ISD::LOAD, VT, Promote);
99 setOperationAction(ISD::STORE, VT, Promote);
133 // Promote all bit-wise operations.
135 setOperationAction(ISD::AND, VT, Promote);
137 setOperationAction(ISD::OR, VT, Promote);
139 setOperationAction(ISD::XOR, VT, Promote);
621 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
