| /external/llvm/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 65 // Compute all information about RC.
66 void compute(const TargetRegisterClass *RC) const;
68 // Return an up-to-date RCInfo for RC.
69 const RCInfo &get(const TargetRegisterClass *RC) const {
70 const RCInfo &RCI = RegClass[RC->getID()];
72 compute(RC);
84 /// registers in RC in the current function.
85 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
86 return get(RC).NumRegs;
89 /// getOrder - Returns the preferred allocation order for RC. The orde
[all...] |
| FastISel.h | 260 const TargetRegisterClass *RC);
266 const TargetRegisterClass *RC,
273 const TargetRegisterClass *RC,
281 const TargetRegisterClass *RC,
290 const TargetRegisterClass *RC,
298 const TargetRegisterClass *RC,
306 const TargetRegisterClass *RC,
314 const TargetRegisterClass *RC,
323 const TargetRegisterClass *RC,
331 const TargetRegisterClass *RC,
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| /external/llvm/lib/Target/NVPTX/ |
| NVPTXRegisterInfo.cpp | 31 std::string getNVPTXRegClassName (TargetRegisterClass const *RC) {
32 if (RC == &NVPTX::Float32RegsRegClass) {
35 if (RC == &NVPTX::Float64RegsRegClass) {
38 else if (RC == &NVPTX::Int64RegsRegClass) {
41 else if (RC == &NVPTX::Int32RegsRegClass) {
44 else if (RC == &NVPTX::Int16RegsRegClass) {
48 else if (RC == &NVPTX::Int8RegsRegClass) {
51 else if (RC == &NVPTX::Int1RegsRegClass) {
54 else if (RC == &NVPTX::SpecialRegsRegClass) {
63 std::string getNVPTXRegClassStr (TargetRegisterClass const *RC) {
[all...] |
| NVPTXRegisterInfo.h | 78 std::string getNVPTXRegClassName (const TargetRegisterClass *RC);
79 std::string getNVPTXRegClassStr (const TargetRegisterClass *RC);
|
| /external/llvm/lib/Target/Mips/ |
| MipsMachineFunction.cpp | 36 const TargetRegisterClass *RC;
38 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
40 RC = ST.isABI_N64() ?
43 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
54 const TargetRegisterClass *RC;
55 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
56 return Mips16SPAliasReg = MF.getRegInfo().createVirtualRegister(RC);
62 const TargetRegisterClass *RC = ST.isABI_N64() ?
65 EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
66 RC->getAlignment(), false)
[all...] |
| Mips16RegisterInfo.h | 37 const TargetRegisterClass *RC,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.h | 51 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
53 /// getLargestLegalSuperClass - Returns the largest super class of RC that is
56 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
57 if (RC == &AArch64::tcGPR64RegClass)
60 return RC;
|
| /external/llvm/lib/CodeGen/ |
| LiveStackAnalysis.cpp | 58 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
64 S2RCMap.insert(std::make_pair(Slot, RC));
68 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
80 const TargetRegisterClass *RC = getIntervalRegClass(Slot);
81 if (RC)
82 OS << " [" << RC->getName() << "]\n";
|
| TargetRegisterInfo.cpp | 77 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
78 if (!RC || RC->isAllocatable())
79 return RC;
81 const unsigned *SubClass = RC->getSubClassMask();
108 const TargetRegisterClass* RC = *I;
109 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
110 (!BestRC || BestRC->hasSubClass(RC)))
111 BestRC = RC;
[all...] |
| RegisterClassInfo.cpp | 72 /// compute - Compute the preferred allocation order for RC with reserved
75 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
76 RCInfo &RCI = RegClass[RC->getID()];
79 unsigned NumRegs = RC->getNumRegs();
92 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
128 // Check if RC is a proper sub-class.
129 if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
130 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
137 dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
|
| RegisterScavenging.cpp | 226 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
227 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
239 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) {
241 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
329 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
334 TRI->getAllocatableSet(*I->getParent()->getParent(), RC);
348 BitVector Available = getRegsAvailable(RC);
371 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg))
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 125 bool hasSubClass(const TargetRegisterClass *RC) const {
126 return RC != this && hasSubClassEq(RC);
129 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
131 bool hasSubClassEq(const TargetRegisterClass *RC) const {
132 unsigned ID = RC->getID();
138 bool hasSuperClass(const TargetRegisterClass *RC) const {
139 return RC->hasSubClass(this);
142 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
144 bool hasSuperClassEq(const TargetRegisterClass *RC) const
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| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.h | 49 const TargetRegisterClass *RC,
55 const TargetRegisterClass *RC,
|
| Thumb1InstrInfo.cpp | 54 const TargetRegisterClass *RC,
56 assert((RC == &ARM::tGPRRegClass ||
60 if (RC == &ARM::tGPRRegClass ||
82 const TargetRegisterClass *RC,
84 assert((RC == &ARM::tGPRRegClass ||
88 if (RC == &ARM::tGPRRegClass ||
|
| Thumb1RegisterInfo.h | 31 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
57 const TargetRegisterClass *RC,
|
| Thumb2InstrInfo.h | 51 const TargetRegisterClass *RC,
57 const TargetRegisterClass *RC,
|
| ARMBaseRegisterInfo.h | 106 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
109 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
111 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
123 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;
|
| /external/llvm/utils/release/ |
| test-release.sh | 28 RC=""
42 echo "usage: `basename $0` -release X.Y -rc NUM [OPTIONS]"
45 echo " -rc NUM The pre-release candidate number."
68 -rc | --rc | -RC | --RC )
70 RC="rc$1"
73 RC=fina
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| /external/llvm/lib/Target/R600/ |
| R600RegisterInfo.h | 34 /// \param RC is an AMDIL reg class.
36 /// \returns the R600 reg class that is equivalent to \p RC.
38 const TargetRegisterClass *RC) const;
|
| SIRegisterInfo.h | 34 /// \param RC is an AMDIL reg class.
36 /// \returns the SI register class that is equivalent to \p RC.
38 getISARegClass(const TargetRegisterClass *RC) const;
|
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.h | 80 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const;
83 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
94 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
96 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
|
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 169 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
172 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i];
173 const CodeGenRegister::Set &Regs = RC.getMembers();
178 RC.buildRegUnitSet(RegUnits);
182 OS << "}, \t// " << RC.getName() << "\n";
185 << " return RCWeightTable[RC->getID()];\n"
281 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
287 << " unsigned SetListStart = RCSetStartTable[RC->getID()];\n"
845 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
[all...] |
| /external/llvm/include/llvm/IR/ |
| InlineAsm.h | 254 static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) {
255 // Store RC + 1, reserve the value 0 to mean 'no register class'.
256 ++RC;
257 assert(RC <= 0x7fff && "Too large register class ID");
259 return InputFlag | (RC << 16);
292 /// class constraint. Sets RC to the register class ID.
293 static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) {
298 // stores RC + 1.
301 RC = High - 1;
|
| /external/clang/lib/AST/ |
| RawCommentList.cpp | 206 void RawCommentList::addComment(const RawComment &RC,
208 if (RC.isInvalid())
215 RC.getSourceRange().getBegin())) {
224 RC.getSourceRange().getBegin()))
228 PrevCommentEndLoc = RC.getSourceRange().getEnd();
231 if (RC.isOrdinary())
237 Comments.push_back(new (Allocator) RawComment(RC));
243 const RawComment &C2 = RC;
261 Comments.push_back(new (Allocator) RawComment(RC));
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.h | 73 const TargetRegisterClass *RC,
78 const TargetRegisterClass *RC,
131 const TargetRegisterClass *RC,
137 const TargetRegisterClass *RC,
|
