| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 195 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
197 SDIVREM, UDIVREM,
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDILISelLowering.cpp | 135 setOperationAction(ISD::SDIVREM, VT, Expand);
155 setOperationAction(ISD::SDIVREM, VT, Expand);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 167 case ISD::SDIVREM: return "sdivrem";
|
| LegalizeDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 158 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
164 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 104 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 381 setTargetDAGCombine(ISD::SDIVREM);
592 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 718 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 134 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
135 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 125 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
131 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
133 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
376 setOperationAction(ISD::SDIVREM, VT, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 686 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
[all...] |
