| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 65 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
66 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
95 setTargetDAGCombine(ISD::SELECT_CC);
315 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
548 // select_cc f32, f32, -1, 0, cc_any
549 // select_cc f32, f32, 1.0f, 0.0f, cc_any
550 // select_cc i32, i32, -1, 0, cc_any
563 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
570 // select_cc f32, 0.0, f32, f32, cc_any
571 // select_cc f32, 0.0, i32, i32, cc_an
[all...] |
| SIISelLowering.cpp | 69 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
70 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
72 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
73 setTargetDAGCombine(ISD::SELECT_CC);
249 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
379 case ISD::SELECT_CC: {
|
| AMDILISelLowering.cpp | 158 setOperationAction(ISD::SELECT_CC, VT, Expand);
268 case ISD::SELECT_CC:
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 343 SELECT_CC,
500 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
[all...] |
| SelectionDAG.h | 625 return getNode(ISD::SELECT_CC, DL, True.getValueType(),
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 60 /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
62 SELECT_CC,
|
| MSP430ISelLowering.cpp | 116 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
117 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
197 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 68 /// This is an A64-ification of the standard LLVM SELECT_CC operation. The
71 SELECT_CC,
75 /// compare after we've moved the CondCode information onto the SELECT_CC or
|
| AArch64ISelLowering.cpp | 101 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
102 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
103 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
104 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
229 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
775 case AArch64ISD::SELECT_CC: return "AArch64ISD::SELECT_CC";
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 97 case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N); break;
536 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
615 case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break;
[all...] |
| LegalizeTypesGeneric.cpp | 514 Lo = DAG.getNode(ISD::SELECT_CC, dl, LL.getValueType(), N->getOperand(0),
516 Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0),
|
| SelectionDAGDumper.cpp | 191 case ISD::SELECT_CC: return "select_cc";
|
| LegalizeVectorTypes.cpp | 63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
291 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
498 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
[all...] |
| LegalizeVectorOps.cpp | 220 case ISD::SELECT_CC:
|
| LegalizeIntegerTypes.cpp | 69 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
505 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
[all...] |
| DAGCombiner.cpp | 540 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
553 if (N.getOpcode() == ISD::SELECT_CC &&
[all...] |
| LegalizeDAG.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 50 case MBlazeISD::Select_CC : return "MBlazeISD::Select_CC";
130 // Expand SELECT_CC
131 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
145 AddPromotedToType(ISD::SELECT_CC, MVT::i1, MVT::i32);
207 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
229 case MBlaze::Select_CC:
355 // To "insert" a SELECT_CC instruction, we actually have to insert the
583 Opc = MBlazeISD::Select_CC;
587 llvm_unreachable("Cannot lower select_cc with unknown type")
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 732 // Sparc has no select or setcc: expand to SELECT_CC.
748 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
749 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
750 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 88 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
95 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
181 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 235 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
236 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
284 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 124 setOperationAction(ISD::SELECT_CC, VT, Expand);
590 setTargetDAGCombine(ISD::SELECT_CC);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 103 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
[all...] |
