| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | [all...] |
| /external/llvm/lib/CodeGen/ |
| Analysis.cpp | 176 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT;
195 case ICmpInst::ICMP_SLT: return ISD::SETLT;
|
| TargetLoweringBase.cpp | 602 CCs[RTLIB::OLT_F32] = ISD::SETLT;
603 CCs[RTLIB::OLT_F64] = ISD::SETLT;
604 CCs[RTLIB::OLT_F128] = ISD::SETLT;
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDILISelLowering.cpp | 508 ISD::SETLT);
515 ISD::SETLT);
610 SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT);
613 SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT);
|
| AMDGPUISelLowering.cpp | 216 case ISD::SETLT: {
|
| R600ISelLowering.cpp | 600 case ISD::SETLT:
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 585 case ISD::SETLT: return PPC::PRED_LT;
612 case ISD::SETLT: return 0; // Bit #0 = SETOLT
655 case ISD::SETLT:
746 case ISD::SETLT: {
779 case ISD::SETLT: {
819 case ISD::SETLT:
[all...] |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 127 case ISD::SETLT:
[all...] |
| SelectionDAGDumper.cpp | 308 case ISD::SETLT: return "setlt";
|
| LegalizeIntegerTypes.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| SelectionDAG.cpp | 257 case ISD::SETLT:
[all...] |
| LegalizeFloatTypes.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 651 case ISD::SETLT: return SPCC::ICC_L;
671 case ISD::SETLT:
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 761 case ISD::SETLT:
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 626 case ISD::SETLT:
[all...] |
