| /external/skia/gm/ |
| strokerects.cpp | 21 static const SkScalar SH = SkIntToScalar(H);
58 canvas->translate(SW * x, SH * y);
61 , SW - SkIntToScalar(2), SH - SkIntToScalar(2)
|
| strokes.cpp | 19 static const SkScalar SH = SkIntToScalar(H);
58 canvas->translate(0, SH * y);
61 , SW - SkIntToScalar(2), SH - SkIntToScalar(2)
118 canvas->translate(0, SH * y);
122 SH - SkIntToScalar(2)));
128 rotate(SkIntToScalar(15), SW/2, SH/2, canvas);
|
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| PPCInstPrinter.cpp | 34 unsigned char SH = MI->getOperand(2).getImm();
38 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
41 if (SH <= 31 && MB == (32-SH) && ME == 31) {
43 SH = 32-SH;
49 O << ", " << (unsigned int)SH;
67 unsigned char SH = MI->getOperand(2).getImm();
69 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, S
[all...] |
| /external/qemu/tcg/ppc/ |
| tcg-target.c | 400 #define SH(s) ((s)<<11)
559 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
574 | SH (0)
755 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
770 | SH (0)
807 | SH (0)
815 | SH (0)
1125 int crop, sh, arg; local
1152 | SH (27)
1192 sh = 30
[all...] |
| /ndk/sources/host-tools/sed-4.2.1/doc/ |
| sed.x | 1 .SH NAME
3 .SH SYNOPSIS
194 .SH
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCJITInfo.cpp | 33 #define BUILD_RLDICR(RD,RS,SH,ME) \
34 ((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \
35 (((ME) & 63) << 6) | (1 << 2) | ((((SH) >> 5) & 1) << 1))
|
| PPCISelDAGToDAG.cpp | 99 unsigned &SH, unsigned &MB, unsigned &ME);
360 bool isShiftMask, unsigned &SH,
394 SH = Shift & 31;
418 unsigned Value, SH = 0;
450 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
457 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
463 SH &= 31;
464 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
[all...] |
| /external/srec/config/en.us/dictionary/ |
| c0.6 | 50 "!EXCLAMATION-POINT EH2 K S K L AH0 M EY1 SH AH0 N P OY2 N T
58 #SHARP-SIGN SH AA1 R P S AY1 N
94 -DASH D AE1 SH
102 /SLASH S L AE1 SH
159 ABASH AH0 B AE1 SH
160 ABASHED AH0 B AE1 SH T
191 ABBREVIATION AH0 B R IY2 V IY0 EY1 SH AH0 N
192 ABBREVIATIONS AH0 B R IY2 V IY0 EY1 SH AH0 N Z
206 ABDICATION AE2 B D IH0 K EY1 SH AH0 N
221 ABDUCTION AE0 B D AH1 K SH AH0
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| ScalarEvolutionExpander.h | 139 Value *expandCodeFor(const SCEV *SH, Type *Ty, Instruction *I);
222 Value *expandCodeFor(const SCEV *SH, Type *Ty = 0);
|
| /external/v8/src/mips/ |
| constants-mips.cc | 331 case SH:
|
| constants-mips.h | 289 SH = ((5 << 3) + 1) << kOpcodeShift,
|
| /external/strace/linux/ |
| syscall.h | 176 # elif defined SH
329 #if defined M68K || defined SH
|
| /external/qemu/tcg/ppc64/ |
| tcg-target.c | 397 #define SH(s) ((s)<<11)
443 static void tcg_out_rld (TCGContext *s, int op, int ra, int rs, int sh, int mb)
445 sh = SH (sh & 0x1f) | (((sh >> 5) & 1) << 1);
447 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
578 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
588 | SH (0)
1053 int crop, sh, arg local
1479 int sh = SH (args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1); local
[all...] |
| /external/strace/ |
| defs.h | 407 || defined(SH) || defined(SH64) || defined(S390) || defined(S390X) \
607 && !defined(SH))
|
| sock.c | 41 #if defined (ALPHA) || defined(SH) || defined(SH64)
|
| io.c | 274 #if defined(SH)
|
| syscall.c | 716 #elif defined(SH)
1227 # elif defined(SH)
1290 #elif defined(SH)
[all...] |
| mem.c | 292 #elif defined(SH) || defined(SH64)
293 /* SH has always passed the args in registers */
|
| /external/libffi/ |
| Makefile.am | 24 src/sh/ffi.c src/sh/sysv.S src/sh/ffitarget.h \
150 if SH
151 nodist_libffi_la_SOURCES += src/sh/sysv.S src/sh/ffi.c
|
| /external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/ |
| org.apache.lucene.analysis_1.9.1.v20100518-1140.jar | |
| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 53 MBlaze::SB, MBlaze::SH, MBlaze::SW, UNSUPPORTED, //34,35,36,37
395 case 0x0: return MBlaze::SH;
481 case MBlaze::SH: return decodeSH(insn);
|
| /external/llvm/lib/Analysis/ |
| ScalarEvolutionExpander.cpp | [all...] |
| /external/qemu/ |
| ppc-dis.c | 753 /* The SH field in an X or M form instruction. */
754 #define SH RSO + 1
757 #define EVUIMM SH
760 /* The SH field in an MD form instruction. This is split. */
761 #define SH6 SH + 1
765 /* The SH field of the tlbwe instruction, which is optional. */
883 /* SH field starting at bit position 16. */
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 947 mMips->SH(Rd, Rn, amode.value);
950 mMips->SH(Rd, Rn, 0);
960 mMips->SH(Rd, R_at, 0);
[all...] |
| MIPSAssembler.h | 341 void SH(int Rt, int Rbase, int16_t offset);
|
