| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 382 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
387 SIGN_EXTEND_INREG,
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDILISelLowering.cpp | 98 //FIXME: SIGN_EXTEND_INREG is not meaningful for floating point types
100 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
199 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);
206 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
|
| AMDGPUISelLowering.cpp | 103 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 64 // Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
248 case ISD::SIGN_EXTEND_INREG:
286 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG)
|
| LegalizeIntegerTypes.cpp | 72 case ISD::SIGN_EXTEND_INREG:
399 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
464 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
542 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
674 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
[all...] |
| SelectionDAGDumper.cpp | 218 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
|
| LegalizeVectorTypes.cpp | 60 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
272 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), CondVT,
508 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
[all...] |
| SelectionDAG.cpp | [all...] |
| LegalizeTypes.h | 200 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
[all...] |
| DAGCombiner.cpp | 767 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
779 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
[all...] |
| LegalizeDAG.cpp | [all...] |
| TargetLowering.cpp | 732 case ISD::SIGN_EXTEND_INREG: {
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 111 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Expand);
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
114 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 711 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
712 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
713 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 140 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 388 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
389 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
390 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
391 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 289 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
358 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
359 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 859 if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
[all...] |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 126 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 207 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
385 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
[all...] |
