| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 223 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
226 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
228 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
230 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
232 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
234 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
236 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
238 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
240 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
242 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }
[all...] |
| ARMISelLowering.cpp | 109 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
114 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
555 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
559 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 379 SINT_TO_FP,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 254 case ISD::SINT_TO_FP:
268 case ISD::SINT_TO_FP:
698 // Make sure that the SINT_TO_FP and SRL instructions are available.
699 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
725 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
727 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
|
| LegalizeFloatTypes.cpp | 98 case ISD::SINT_TO_FP:
564 bool Signed = N->getOpcode() == ISD::SINT_TO_FP;
[all...] |
| SelectionDAGDumper.cpp | 225 case ISD::SINT_TO_FP: return "sint_to_fp";
|
| LegalizeDAG.cpp | [all...] |
| LegalizeVectorTypes.cpp | 90 case ISD::SINT_TO_FP:
546 case ISD::SINT_TO_FP:
[all...] |
| FastISel.cpp | 224 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
[all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 251 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
252 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 },
|
| X86ISelLowering.cpp | 255 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
273 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
275 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
276 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
283 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
286 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
289 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| AMDILISelLowering.cpp | 434 SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia);
437 SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);
|
| R600ISelLowering.cpp | 47 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 723 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 240 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
241 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
242 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 198 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
287 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
296 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
409 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
468 setTargetDAGCombine(ISD::SINT_TO_FP);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
