| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.h | 64 int SPAdj, RegScavenger *RS) const;
66 int SPAdj, RegScavenger *RS) const;
68 int SPAdj, RegScavenger *RS) const;
72 int SPAdj, unsigned FIOperandNum,
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| PPCRegisterInfo.cpp | 178 int SPAdj, RegScavenger *RS) const {
274 unsigned FrameIndex, int SPAdj,
285 (void) SPAdj;
316 unsigned FrameIndex, int SPAdj,
327 (void) SPAdj;
379 int SPAdj, unsigned FIOperandNum,
381 assert(SPAdj == 0 && "Unexpected");
412 lowerDynamicAlloc(II, SPAdj, RS);
418 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
421 lowerCRRestore(II, FrameIndex, SPAdj, RS)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 116 /// available and do the appropriate bookkeeping. SPAdj is the stack
120 MachineBasicBlock::iterator I, int SPAdj);
121 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
122 return scavengeRegister(RegClass, MBBI, SPAdj);
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeRegisterInfo.h | 55 int SPAdj, unsigned FIOperandNum,
|
| MBlazeRegisterInfo.cpp | 90 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.h | 46 int SPAdj, unsigned FIOperandNum,
|
| MSP430RegisterInfo.cpp | 106 int SPAdj, unsigned FIOperandNum,
108 assert(SPAdj == 0 && "Unexpected");
|
| /external/llvm/lib/Target/R600/ |
| AMDGPURegisterInfo.h | 55 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
| AMDGPURegisterInfo.cpp | 40 int SPAdj,
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.h | 40 int SPAdj, unsigned FIOperandNum,
|
| SparcRegisterInfo.cpp | 61 int SPAdj, unsigned FIOperandNum,
63 assert(SPAdj == 0 && "Unexpected");
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.h | 43 void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
| AArch64RegisterInfo.cpp | 82 int SPAdj,
85 assert(SPAdj == 0 && "Cannot deal with nonzero SPAdj yet");
112 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj,
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| AArch64FrameLowering.h | 59 unsigned &FrameReg, int SPAdj,
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1RegisterInfo.h | 60 int SPAdj, unsigned FIOperandNum,
|
| ARMFrameLowering.h | 56 unsigned &FrameReg, int SPAdj) const;
|
| ARMBaseRegisterInfo.h | 172 int SPAdj, unsigned FIOperandNum,
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.h | 60 int SPAdj, unsigned FIOperandNum,
|
| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.h | 58 int SPAdj, unsigned FIOperandNum,
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXRegisterInfo.h | 58 int SPAdj, unsigned FIOperandNum,
|
| NVPTXRegisterInfo.cpp | 124 int SPAdj, unsigned FIOperandNum,
126 assert(SPAdj == 0 && "Unexpected");
|
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.h | 58 int SPAdj, unsigned FIOperandNum,
|
| XCoreRegisterInfo.cpp | 106 int SPAdj, unsigned FIOperandNum,
108 assert(SPAdj == 0 && "Unexpected");
167 SPAdj);
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| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.h | 121 int SPAdj, unsigned FIOperandNum,
|
| /external/llvm/lib/CodeGen/ |
| RegisterScavenging.cpp | 331 int SPAdj) {
379 TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
386 TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
|
