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    Searched refs:SRC1 (Results 1 - 7 of 7) sorted by null

  /external/bison/lib/
bitset.h 217 /* DST = SRC1 & SRC2. */
218 #define bitset_and(DST, SRC1, SRC2) BITSET_AND_ (DST, SRC1, SRC2)
220 /* DST = SRC1 & SRC2. Return non-zero if DST != SRC1 & SRC2. */
221 #define bitset_and_cmp(DST, SRC1, SRC2) BITSET_AND_CMP_ (DST, SRC1, SRC2)
223 /* DST = SRC1 & ~SRC2. */
224 #define bitset_andn(DST, SRC1, SRC2) BITSET_ANDN_ (DST, SRC1, SRC2
    [all...]
bbitset.h 164 #define BITSET_CHECK3_(DST, SRC1, SRC2) \
165 if (!BITSET_COMPATIBLE_ (DST, SRC1) \
168 #define BITSET_CHECK4_(DST, SRC1, SRC2, SRC3) \
169 if (!BITSET_COMPATIBLE_ (DST, SRC1) || !BITSET_COMPATIBLE_ (DST, SRC2) \
229 /* DST = SRC1 & SRC2. */
230 #define BITSET_AND_(DST, SRC1, SRC2) (SRC1)->b.vtable->and_ (DST, SRC1, SRC2)
231 #define BITSET_AND_CMP_(DST, SRC1, SRC2) (SRC1)->b.vtable->and_cmp (DST, SRC1, SRC2
    [all...]
  /external/llvm/lib/Target/R600/
R600Defines.h 69 SRC1,
R600ExpandSpecialInstrs.cpp 81 AMDGPU::ZERO); // src1
224 unsigned Src1 = 0;
228 int Src1Idx = TII->getOperandIdx(MI, R600Operands::SRC1);
230 Src1 = MI.getOperand(Src1Idx).getReg();
236 Src1 = TRI.getSubReg(Src1, SubRegIndex);
241 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
282 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
R600InstrInfo.cpp 175 {R600Operands::SRC1, R600Operands::SRC1_SEL},
673 MIB.addReg(Src1Reg) // $src1
713 case R600Operands::SRC1: return 2;
AMDILISelDAGToDAG.cpp 343 TII->getOperandIdx(Opcode, R600Operands::SRC1),
  /external/llvm/lib/Target/R600/MCTargetDesc/
R600MCCodeEmitter.cpp 221 {R600Operands::SRC1, R600Operands::SRC1_SEL},

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