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    Searched refs:SWI (Results 1 - 12 of 12) sorted by null

  /external/llvm/lib/Target/MBlaze/
MBlazeFrameLowering.cpp 111 // SWI REG, FI2, 0
114 // the SWI instruction because the value has already been stored to the
118 // Additionally, if the SWI operation kills the def of REG then we don't
131 SI->getOpcode() != MBlaze::SWI) continue;
147 DEBUG(dbgs() << "SWI for FI#" << FI << " removed\n");
163 // ... SWI REG, FI, 0
175 if (I->getOpcode() != MBlaze::SWI || I->getNumOperands() != 3 ||
247 // Build the prologue SWI for R3 - R12 if needed. Note that R11 must
248 // always have a SWI because it is used when processing RMSR.
255 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), r
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MBlazeInstrInfo.cpp 64 if (MI->getOpcode() == MBlaze::SWI) {
98 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
  /system/core/libpixelflinger/codeflinger/
ARMAssemblerProxy.h 127 virtual void SWI(int cc, uint32_t comment);
ARMAssemblerProxy.cpp 249 void ARMAssemblerProxy::SWI(int cc, uint32_t comment) {
250 mTarget->SWI(cc, comment);
ARMAssembler.h 140 virtual void SWI(int cc, uint32_t comment);
ARMAssemblerInterface.h 180 virtual void SWI(int cc, uint32_t comment) = 0;
ARMAssembler.cpp 361 void ARMAssembler::SWI(int cc, uint32_t comment) {
MIPSAssembler.h 139 virtual void SWI(int cc, uint32_t comment);
MIPSAssembler.cpp 1019 void ArmToMipsAssembler::SWI(int cc, uint32_t comment) {
    [all...]
  /external/grub/netboot/
sis900.h 43 SWI = 0x00000080,
  /external/llvm/utils/TableGen/
CodeGenSchedule.cpp 284 for (RecIter SWI = SWDefs.begin(), SWE = SWDefs.end(); SWI != SWE; ++SWI) {
285 assert(!getSchedRWIdx(*SWI, /*IsRead=*/false) && "duplicate SchedWrite");
286 SchedWrites.push_back(CodeGenSchedRW(SchedWrites.size(), *SWI));
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  /external/llvm/lib/Target/MBlaze/Disassembler/
MBlazeDisassembler.cpp 55 MBlaze::SBI, MBlaze::SHI, MBlaze::SWI, UNSUPPORTED, //3C,3D,3E,3F

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