/external/llvm/lib/Target/Hexagon/ |
HexagonSplitTFRCondSets.cpp | 92 int SrcReg2 = MI->getOperand(3).getReg(); 110 if (DestReg != SrcReg2) { 112 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); 149 int SrcReg2 = MI->getOperand(3).getReg(); 165 if (DestReg != SrcReg2) { 168 addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
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HexagonInstrInfo.h | 70 unsigned &SrcReg, unsigned &SrcReg2,
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HexagonInstrInfo.cpp | 309 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it 313 unsigned &SrcReg, unsigned &SrcReg2, 371 SrcReg2 = MI->getOperand(2).getReg(); 381 SrcReg2 = 0; [all...] |
/external/llvm/lib/CodeGen/ |
PeepholeOptimizer.cpp | 381 unsigned SrcReg, SrcReg2; 383 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) || 385 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2))) 389 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
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/external/llvm/include/llvm/Target/ |
TargetInstrInfo.h | [all...] |
/external/llvm/lib/Target/ARM/ |
ARMBaseInstrInfo.h | 193 /// in SrcReg and SrcReg2 if having two register operands, and the value it 197 unsigned &SrcReg2, int &CmpMask, 205 unsigned SrcReg2, int CmpMask, int CmpValue,
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ARMBaseInstrInfo.cpp | [all...] |
ARMFastISel.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrInfo.h | 379 /// in SrcReg and SrcReg2 if having two register operands, and the value it 383 unsigned &SrcReg2, 390 unsigned SrcReg2, int CmpMask, int CmpValue,
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X86InstrInfo.cpp | [all...] |