| /external/llvm/lib/Transforms/Scalar/ |
| Sink.cpp | 57 bool SinkInstruction(Instruction *I, SmallPtrSet<Instruction *, 8> &Stores);
134 SmallPtrSet<Instruction *, 8> Stores;
147 if (SinkInstruction(Inst, Stores))
157 SmallPtrSet<Instruction *, 8> &Stores) {
160 Stores.insert(Inst);
166 for (SmallPtrSet<Instruction *, 8>::iterator I = Stores.begin(),
167 E = Stores.end(); I != E; ++I)
195 // We cannot sink a load across a critical edge - there may be stores in
220 SmallPtrSet<Instruction *, 8> &Stores) {
222 if (!isSafeToMove(Inst, AA, Stores))
[all...] |
| /external/oprofile/events/mips/r10000/ |
| events | 11 event:0x03 counters:0 um:zero minimum:500 name:STORES_ISSUED : Stores issued
12 event:0x03 counters:1 um:zero minimum:500 name:STORES_GRADUATED : Stores graduated
34 event:0x0e counters:1 um:zero minimum:500 name:STORES_OR_STORE_PREF_TO_CLEANEXCLUSIVE_SCACHE_BLOCKS : Stores or prefetches with store hint to CleanExclusive secondary cache blocks
36 event:0x0f counters:1 um:zero minimum:500 name:STORES_OR_STORE_PREF_TO_SHD_SCACHE_BLOCKS : Stores or prefetches with store hint to Shared secondary cache blocks
|
| /external/oprofile/events/mips/5K/ |
| events | 10 event:0x3 counters:0,1 um:zero minimum:500 name:STORES_EXECED : Stores (including conditional stores) executed
11 event:0x4 counters:0,1 um:zero minimum:500 name:COND_STORES_EXECED : Conditional stores executed
17 event:0x5 counters:0 um:zero minimum:500 name:FAILED_COND_STORES : Failed conditional stores
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 551 SmallVector<SDValue, 8> Stores;
564 Stores.push_back(Store);
567 &Stores[0], Stores.size());
|
| LegalizeDAG.cpp | 299 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
304 "unaligned indexed stores not implemented!");
317 // FIXME: Does not handle truncating floating point stores!
325 // to the final destination using (unaligned) integer loads and stores.
343 SmallVector<SDValue, 8> Stores;
353 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
375 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
381 // The order of the stores doesn't matter - say it with a TokenFactor.
383 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
384 Stores.size())
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 75 // Legalize loads and stores to the private address space.
729 assert(!"Truncated and indexed stores not supported yet");
754 SDValue Stores[4];
767 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
771 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores, NumElemVT);
[all...] |
| /external/oprofile/events/mips/24K/ |
| events | 31 event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
96 event:0x40e counters:1 um:zero minimum:500 name:FPU_INSNS : 14-1 FPU instructions completed (not including loads/stores)
97 event:0x40f counters:1 um:zero minimum:500 name:STORE_INSNS : 15-1 Stores completed (including FP)
114 event:0x423 counters:1 um:zero minimum:500 name:CP2_TO_FROM_INSNS : 35-1 CP2 to/from instructions (moves, control, loads, stores)
|
| /external/oprofile/events/mips/34K/ |
| events | 31 event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
104 event:0x40e counters:1 um:zero minimum:500 name:FPU_INSNS : 14-1 FPU instructions completed (not including loads/stores)
105 event:0x40f counters:1 um:zero minimum:500 name:STORE_INSNS : 15-1 Stores completed (including FP)
125 event:0x423 counters:1 um:zero minimum:500 name:CP2_TO_FROM_INSNS : 35-1 CP2 to/from instructions (moves, control, loads, stores)
|
| /external/llvm/lib/Transforms/Vectorize/ |
| LoopVectorize.cpp | 260 /// The unroll factor. Each entry in the map stores this number of vector
420 /// Alias(Multi)Map stores the values (GEPs or underlying objects and their
[all...] |
| /external/oprofile/events/mips/1004K/ |
| events | 31 event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
112 event:0x40e counters:1 um:zero minimum:500 name:FPU_INSNS : 14-1 FPU instructions completed (not including loads/stores)
113 event:0x40f counters:1 um:zero minimum:500 name:STORE_INSNS : 15-1 Stores completed (including FP)
133 event:0x423 counters:1 um:zero minimum:500 name:CP2_TO_FROM_INSNS : 35-1 CP2 to/from instructions (moves, control, loads, stores)
|
| /external/chromium/chrome/browser/resources/ |
| new_new_tab.js | 367 // Stores some information about each section necessary to layout. A new
[all...] |
| /external/eigen/blas/testing/ |
| cblat2.f | [all...] |
| dblat2.f | [all...] |
| dblat3.f | [all...] |
| sblat2.f | [all...] |
| sblat3.f | [all...] |
| zblat2.f | [all...] |
| cblat3.f | [all...] |
| zblat3.f | [all...] |
