| /external/qemu/tcg/sparc/ |
| tcg-target.h | 134 #define TCG_AREG0 TCG_REG_G2
136 #define TCG_AREG0 TCG_REG_G5
138 #define TCG_AREG0 TCG_REG_G6
|
| tcg-target.c | 781 tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
811 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
814 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
993 tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
1026 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1029 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
[all...] |
| /external/qemu/tcg/ppc64/ |
| tcg-target.h | 106 #define TCG_AREG0 TCG_REG_R27
|
| tcg-target.c | 583 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
601 tcg_out32 (s, ADD | TAB (r0, r0, TCG_AREG0));
[all...] |
| /external/qemu/tcg/i386/ |
| tcg-target.h | 119 #define TCG_AREG0 TCG_REG_R14
123 #define TCG_AREG0 TCG_REG_EBP
|
| tcg-target.c | 1028 tcg_out_modrm_sib_offset(s, OPC_LEA + P_REXW, r1, TCG_AREG0, r1, 0,
[all...] |
| /external/qemu/tcg/arm/ |
| tcg-target.h | 80 TCG_AREG0 = TCG_REG_R7,
|
| tcg-target.c | 997 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0,
[all...] |
| /external/qemu/tcg/ppc/ |
| tcg-target.h | 96 #define TCG_AREG0 TCG_REG_R27
|
| tcg-target.c | 564 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
760 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
[all...] |
| /external/qemu/tcg/x86_64/ |
| tcg-target.h | 89 #define TCG_AREG0 TCG_REG_R14
|
| tcg-target.c | 596 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
791 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
[all...] |
| /external/qemu/tcg/hppa/ |
| tcg-target.h | 106 #define TCG_AREG0 TCG_REG_R17
|
| tcg-target.c | 914 tcg_out_arith(s, r1, r1, TCG_AREG0, INSN_ADDL);
[all...] |
| /external/qemu/ |
| translate-all.c | 89 tcg_set_frame(&tcg_ctx, TCG_AREG0, offsetof(CPUState, temp_buf),
|
| /external/qemu/target-mips/ |
| translate.c | [all...] |
| /external/qemu/target-i386/ |
| translate.c | [all...] |
| /external/qemu/target-arm/ |
| translate.c | 117 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
120 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
124 cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
126 cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
128 cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
131 cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
133 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
[all...] |
