| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 224 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
227 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
229 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
231 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
233 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
235 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
237 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
239 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
241 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
243 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }
[all...] |
| ARMISelLowering.cpp | 110 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
115 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
555 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
560 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 380 UINT_TO_FP,
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 253 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
254 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 },
|
| X86ISelLowering.cpp | 255 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
257 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
258 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
259 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
262 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
263 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
267 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
270 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 255 case ISD::UINT_TO_FP:
269 case ISD::UINT_TO_FP:
292 else if (Node->getOpcode() == ISD::UINT_TO_FP)
363 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
705 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
|
| SelectionDAGDumper.cpp | 226 case ISD::UINT_TO_FP: return "uint_to_fp";
|
| LegalizeVectorTypes.cpp | 92 case ISD::UINT_TO_FP:
548 case ISD::UINT_TO_FP:
[all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeFloatTypes.cpp | 99 case ISD::UINT_TO_FP: R = SoftenFloatRes_XINT_TO_FP(N); break;
[all...] |
| DAGCombiner.cpp | [all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 74 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Expand);
75 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Expand);
76 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 48 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 243 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
244 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
245 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 727 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 285 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
286 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 199 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
288 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
410 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
[all...] |
