| /external/llvm/include/llvm/MC/ |
| MCSubtargetInfo.h | 110 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
117 if (I->UseIdx < UseIdx)
119 if (I->UseIdx > UseIdx)
|
| MCInstrItineraries.h | 202 /// itinerary class UseClass, operand index UseIdx.
204 unsigned UseClass, unsigned UseIdx) const {
214 if ((FirstUseIdx + UseIdx) >= LastUseIdx)
218 Forwardings[FirstUseIdx + UseIdx];
225 unsigned UseClass, unsigned UseIdx) const {
233 int UseCycle = getOperandCycle(UseClass, UseIdx);
239 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
|
| MCSchedule.h | 76 /// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
79 unsigned UseIdx;
84 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
|
| /external/llvm/lib/CodeGen/ |
| LiveRangeEdit.cpp | 77 /// OrigIdx are also available with the same value at UseIdx.
80 SlotIndex UseIdx) {
82 UseIdx = UseIdx.getRegSlot(true);
103 if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
106 if (OVNI != li.getVNInfoAt(UseIdx))
113 SlotIndex UseIdx,
136 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
|
| TargetSchedule.cpp | 166 unsigned UseIdx = 0;
170 ++UseIdx;
172 return UseIdx;
228 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
229 return Latency - STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
|
| TargetInstrInfo.cpp | 576 SDNode *UseNode, unsigned UseIdx) const {
587 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
661 const MachineInstr *UseMI, unsigned UseIdx) const {
664 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
708 /// UseIdx to compute min latency.
712 const MachineInstr *UseMI, unsigned UseIdx,
723 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
|
| SplitKit.h | 313 /// defFromParent - Define Reg from ParentVNI at UseIdx using either
317 SlotIndex UseIdx,
|
| InlineSpiller.cpp | 835 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
836 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
845 DEBUG(dbgs() << UseIdx << '\t' << *MI);
857 if (!Edit->canRematerializeAt(RM, UseIdx, false)) {
859 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
870 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
[all...] |
| MachineVerifier.cpp | [all...] |
| RegisterCoalescer.cpp | 630 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
631 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
682 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
683 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
702 SlotIndex DefIdx = UseIdx.getRegSlot();
[all...] |
| MachineInstr.cpp | [all...] |
| TwoAddressInstructionPass.cpp | 369 SlotIndex useIdx = LIS->getInstructionIndex(MI);
370 LiveInterval::const_iterator I = LI.find(useIdx);
372 return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
[all...] |
| SplitKit.cpp | 430 SlotIndex UseIdx,
443 if (Edit->canRematerializeAt(RM, UseIdx, true)) {
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 226 const MachineInstr *UseMI, unsigned UseIdx) const;
230 SDNode *UseNode, unsigned UseIdx) const;
258 unsigned UseIdx, unsigned UseAlign) const;
262 unsigned UseIdx, unsigned UseAlign) const;
267 unsigned UseIdx, unsigned UseAlign) const;
279 const MachineInstr *UseMI, unsigned UseIdx) const;
|
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveRangeEdit.h | 84 /// OrigIdx are also available with the same value at UseIdx.
86 SlotIndex UseIdx);
160 /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI.
163 SlotIndex UseIdx,
|
| MachineInstr.h | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /external/llvm/utils/TableGen/ |
| SubtargetEmitter.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 376 const MachineInstr *UseMI, unsigned UseIdx) const;
|
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | [all...] |
