1 /** 2 * @file IA64entry.h 3 * 4 * @remark Copy of source code from linux kernel 5 * @remark linux/arch/ia64/kernel/entry.h 6 * 7 */ 8 9 #include <linux/config.h> 10 11 /* 12 * Preserved registers that are shared between code in ivt.S and entry.S. Be 13 * careful not to step on these! 14 */ 15 16 #define pKern p2 /**< will leave_kernel return to kernel-mode? */ 17 #define pUser p3 /**< will leave_kernel return to user-mode? */ 18 #define pSys p4 /**< are we processing a (synchronous) system call? */ 19 #define pNonSys p5 /**< complement of pSys */ 20 21 #define PT(f) (IA64_PT_REGS_##f##_OFFSET) 22 #define SW(f) (IA64_SWITCH_STACK_##f##_OFFSET) 23 24 #define PT_REGS_SAVES(off) \ 25 .unwabi @svr4, 'i'; \ 26 .fframe IA64_PT_REGS_SIZE+16+(off); \ 27 .spillsp rp, PT(CR_IIP)+16+(off); \ 28 .spillsp ar.pfs, PT(CR_IFS)+16+(off); \ 29 .spillsp ar.unat, PT(AR_UNAT)+16+(off); \ 30 .spillsp ar.fpsr, PT(AR_FPSR)+16+(off); \ 31 .spillsp pr, PT(PR)+16+(off); 32 33 #define PT_REGS_UNWIND_INFO(off) \ 34 .prologue; \ 35 PT_REGS_SAVES(off); \ 36 .body 37 38 #define SWITCH_STACK_SAVES(off) \ 39 .savesp ar.unat, SW(CALLER_UNAT)+16+(off); \ 40 .savesp ar.fpsr, SW(AR_FPSR)+16+(off); \ 41 .spillsp f2, SW(F2)+16+(off); .spillsp f3, SW(F3)+16+(off); \ 42 .spillsp f4, SW(F4)+16+(off); .spillsp f5, SW(F5)+16+(off); \ 43 .spillsp f16, SW(F16)+16+(off); .spillsp f17, SW(F17)+16+(off); \ 44 .spillsp f18, SW(F18)+16+(off); .spillsp f19, SW(F19)+16+(off); \ 45 .spillsp f20, SW(F20)+16+(off); .spillsp f21, SW(F21)+16+(off); \ 46 .spillsp f22, SW(F22)+16+(off); .spillsp f23, SW(F23)+16+(off); \ 47 .spillsp f24, SW(F24)+16+(off); .spillsp f25, SW(F25)+16+(off); \ 48 .spillsp f26, SW(F26)+16+(off); .spillsp f27, SW(F27)+16+(off); \ 49 .spillsp f28, SW(F28)+16+(off); .spillsp f29, SW(F29)+16+(off); \ 50 .spillsp f30, SW(F30)+16+(off); .spillsp f31, SW(F31)+16+(off); \ 51 .spillsp r4, SW(R4)+16+(off); .spillsp r5, SW(R5)+16+(off); \ 52 .spillsp r6, SW(R6)+16+(off); .spillsp r7, SW(R7)+16+(off); \ 53 .spillsp b0, SW(B0)+16+(off); .spillsp b1, SW(B1)+16+(off); \ 54 .spillsp b2, SW(B2)+16+(off); .spillsp b3, SW(B3)+16+(off); \ 55 .spillsp b4, SW(B4)+16+(off); .spillsp b5, SW(B5)+16+(off); \ 56 .spillsp ar.pfs, SW(AR_PFS)+16+(off); .spillsp ar.lc, SW(AR_LC)+16+(off); \ 57 .spillsp @priunat, SW(AR_UNAT)+16+(off); \ 58 .spillsp ar.rnat, SW(AR_RNAT)+16+(off); \ 59 .spillsp ar.bspstore, SW(AR_BSPSTORE)+16+(off); \ 60 .spillsp pr, SW(PR)+16+(off)) 61 62 #define DO_SAVE_SWITCH_STACK \ 63 movl r28=1f; \ 64 ;; \ 65 .fframe IA64_SWITCH_STACK_SIZE; \ 66 adds sp=-IA64_SWITCH_STACK_SIZE, sp; \ 67 mov.ret.sptk b7=r28, 1f; \ 68 SWITCH_STACK_SAVES(0); \ 69 br.cond.sptk.many save_switch_stack; \ 70 1: 71 72 #define DO_LOAD_SWITCH_STACK \ 73 movl r28=1f; \ 74 ;; \ 75 invala; \ 76 mov.ret.sptk b7=r28, 1f; \ 77 br.cond.sptk.many load_switch_stack; \ 78 1: .restore sp; \ 79 adds sp=IA64_SWITCH_STACK_SIZE, sp 80
