| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 263 MBB.addLiveIn(SuperReg);
271 MBB.addLiveIn(Reg);
317 MBB.addLiveIn(SuperReg);
324 MBB.addLiveIn(Reg);
|
| HexagonCFGOptimizer.cpp | 217 LayoutSucc->addLiveIn(NewLiveIn[i]);
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 100 MF.getRegInfo().addLiveIn(Mips::T9_64);
101 MBB.addLiveIn(Mips::T9_64);
128 MF.getRegInfo().addLiveIn(Mips::T9);
129 MBB.addLiveIn(Mips::T9);
163 MF.getRegInfo().addLiveIn(Mips::V0);
164 MBB.addLiveIn(Mips::V0);
|
| MipsSEFrameLowering.cpp | 127 MBB.addLiveIn(ehDataReg(I));
231 EntryBlock->addLiveIn(Reg);
|
| Mips16FrameLowering.cpp | 122 EntryBlock->addLiveIn(Reg);
|
| /dalvik/dx/src/com/android/dx/ssa/back/ |
| LivenessAnalyzer.java | 219 blockN.addLiveIn(regV);
|
| /external/dexmaker/src/dx/java/com/android/dx/ssa/back/ |
| LivenessAnalyzer.java | 219 blockN.addLiveIn(regV);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 126 MBB.addLiveIn(XCore::LR);
154 MBB.addLiveIn(XCore::LR);
171 MBB.addLiveIn(XCore::R10);
289 MBB.addLiveIn(it->getReg());
|
| /external/llvm/lib/CodeGen/ |
| MachineRegisterInfo.cpp | 329 EntryMBB->addLiveIn(LiveIns[i].first);
333 EntryMBB->addLiveIn(LiveIns[i].first);
|
| VirtRegMap.cpp | 257 LiveIn[i]->addLiveIn(PhysReg);
|
| MachineFunction.cpp | 415 /// addLiveIn - Add the specified physical register as a live-in value and
417 unsigned MachineFunction::addLiveIn(unsigned PReg,
426 MRI.addLiveIn(PReg, VReg);
[all...] |
| PrologEpilogInserter.cpp | 300 EntryBlock->addLiveIn(CSI[i].getReg());
375 MBB->addLiveIn(blockCSI[i].getReg());
[all...] |
| BranchFolding.cpp | 387 NewMBB->addLiveIn(i);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 76 I->addLiveIn(MSP430::FPW);
198 MBB.addLiveIn(Reg);
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 807 I->addLiveIn(FramePtr);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineFunction.h | 308 /// addLiveIn - Add the specified physical register as a live-in value and
310 unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC);
|
| MachineRegisterInfo.h | 470 /// addLiveIn - Add the specified register as a live-in. Note that it
472 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
|
| MachineBasicBlock.h | 292 /// addLiveIn - Add the specified register as a live in. Note that it
294 void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); }
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.cpp | 293 RegInfo.addLiveIn(MBlaze::R20);
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUIndirectAddressing.cpp | 135 (*Succ)->addLiveIn(Key->second);
|
| SIISelLowering.cpp | 169 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
176 Reg = MF.addLiveIn(Reg, RC);
190 Reg = MF.addLiveIn(Reg, RC);
|
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 614 MBB.addLiveIn(Reg);
806 MBB.addLiveIn(SupReg);
[all...] |
| Thumb1FrameLowering.cpp | 359 MBB.addLiveIn(Reg);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 183 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
198 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
209 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
321 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
