| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 30 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
33 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
39 addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
52 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
57 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
59 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
|
| Mips16ISelLowering.cpp | 45 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
46 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
51 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 35 addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass);
36 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
38 addRegisterClass(MVT::v16i8, &AMDGPU::SReg_128RegClass);
39 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
40 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
42 addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass);
43 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
45 addRegisterClass(MVT::v1i32, &AMDGPU::VReg_32RegClass);
47 addRegisterClass(MVT::v2i32, &AMDGPU::VReg_64RegClass);
48 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass)
[all...] |
| R600ISelLowering.cpp | 32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
34 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
35 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 94 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
95 addRegisterClass(MVT::i8, &NVPTX::Int8RegsRegClass);
96 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
97 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
98 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
99 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
100 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 694 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
695 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
696 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 65 addRegisterClass(MVT::i32, &MBlaze::GPRRegClass);
67 addRegisterClass(MVT::f32, &MBlaze::GPRRegClass);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 53 addRegisterClass(MVT::i32, &AArch64::GPR32RegClass);
54 addRegisterClass(MVT::i64, &AArch64::GPR64RegClass);
55 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
56 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
57 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
58 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 231 addRegisterClass(MVT::i8, &X86::GR8RegClass);
232 addRegisterClass(MVT::i16, &X86::GR16RegClass);
233 addRegisterClass(MVT::i32, &X86::GR32RegClass);
235 addRegisterClass(MVT::i64, &X86::GR64RegClass);
602 addRegisterClass(MVT::f32, &X86::FR32RegClass);
603 addRegisterClass(MVT::f64, &X86::FR64RegClass);
636 addRegisterClass(MVT::f32, &X86::FR32RegClass);
637 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
671 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
672 addRegisterClass(MVT::f32, &X86::RFP32RegClass)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 67 addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
68 addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 86 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
87 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
88 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
304 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
416 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
417 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
418 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
419 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 70 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 153 addRegisterClass(VT, &ARM::DPRRegClass);
158 addRegisterClass(VT, &ARM::QPRRegClass);
431 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
433 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
436 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
438 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
[all...] |
