| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.cpp | 341 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_XRegClass);
344 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_YRegClass);
347 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass);
350 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_WRegClass);
|
| /external/llvm/lib/CodeGen/ |
| OptimizePHIs.cpp | 168 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
|
| UnreachableBlockElim.cpp | 201 MRI.constrainRegClass(Input, MRI.getRegClass(Output));
|
| MachineCSE.cpp | 136 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg)))
546 if (!MRI->constrainRegClass(NewReg, OldRC)) {
|
| MachineRegisterInfo.cpp | 45 MachineRegisterInfo::constrainRegClass(unsigned Reg,
|
| PeepholeOptimizer.cpp | 280 MRI->constrainRegClass(DstReg, DstRC);
|
| TailDuplication.cpp | 285 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) {
443 MRI->constrainRegClass(VI->second, MRI->getRegClass(Reg));
[all...] |
| RegisterCoalescer.cpp | 650 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
771 if (!MRI->constrainRegClass(DstReg, RC))
[all...] |
| TwoAddressInstructionPass.cpp | [all...] |
| MachineLICM.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineRegisterInfo.h | 260 /// constrainRegClass(ToReg, getRegClass(FromReg))
305 /// constrainRegClass - Constrain the register class of the specified virtual
312 const TargetRegisterClass *constrainRegClass(unsigned Reg,
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 556 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
|
| ARMLoadStoreOptimizer.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 320 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
432 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
[all...] |
| FastISel.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 366 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
428 MRI.constrainRegClass(scratch, TRCsp);
446 MRI.constrainRegClass(incr, TRCsp);
455 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
523 MRI.constrainRegClass(dest, TRCsp);
536 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
