/external/llvm/lib/Target/ARM/ |
Thumb2RegisterInfo.cpp | 49 .addReg(DestReg, getDefRegState(true), SubIdx)
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ARMBaseInstrInfo.h | 332 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
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ARMLoadStoreOptimizer.cpp | 353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) 778 .addReg(Base, getDefRegState(true)) // WB base register 931 .addReg(Base, getDefRegState(true)) // WB base register 934 .addReg(MO.getReg(), (isLd ? getDefRegState(true) : [all...] |
MLxExpansionPass.cpp | 300 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
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Thumb1FrameLowering.cpp | 396 MIB.addReg(Reg, getDefRegState(true));
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ARMBaseRegisterInfo.cpp | 378 .addReg(DestReg, getDefRegState(true), SubIdx)
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Thumb1RegisterInfo.cpp | 79 .addReg(DestReg, getDefRegState(true), SubIdx)
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ARMFrameLowering.cpp | 697 MIB.addReg(Regs[i], getDefRegState(true)); [all...] |
ARMISelLowering.cpp | [all...] |
/external/llvm/lib/CodeGen/ |
MachineInstrBundle.cpp | 191 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
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/external/llvm/include/llvm/CodeGen/ |
MachineInstrBuilder.h | 338 inline unsigned getDefRegState(bool B) {
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/external/llvm/lib/CodeGen/SelectionDAG/ |
InstrEmitter.cpp | 350 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | [all...] |
/external/llvm/lib/Target/X86/ |
X86FrameLowering.cpp | 175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)); [all...] |
X86InstrInfo.cpp | [all...] |