| /external/llvm/lib/MC/ |
| MCRegisterInfo.cpp | 21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const {
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| /external/llvm/lib/Target/R600/ |
| R600ExpandSpecialInstrs.cpp | 174 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg);
235 Src0 = TRI.getSubReg(Src0, SubRegIndex);
236 Src1 = TRI.getSubReg(Src1, SubRegIndex);
241 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
242 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
250 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
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| SIInstrInfo.cpp | 132 get(Opcode), RI.getSubReg(DestReg, SubIdx));
134 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
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| /external/llvm/lib/CodeGen/ |
| TargetRegisterInfo.cpp | 183 if (RCI.getSubReg() == Idx)
222 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
231 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
241 *BestPreA = IA.getSubReg();
242 *BestPreB = IB.getSubReg();
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| CalcSpillWeights.cpp | 64 sub = mi->getOperand(0).getSubReg();
66 hsub = mi->getOperand(1).getSubReg();
68 sub = mi->getOperand(1).getSubReg();
70 hsub = mi->getOperand(0).getSubReg();
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| OptimizePHIs.cpp | 106 !SrcMI->getOperand(0).getSubReg() &&
107 !SrcMI->getOperand(1).getSubReg() &&
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| TargetInstrInfo.cpp | 138 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0;
139 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg();
140 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
316 if (FoldOp.getSubReg() || LiveOp.getSubReg())
451 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
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| VirtRegMap.cpp | 293 if (MO.getSubReg()) {
315 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
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| ExpandPostRAPseudos.cpp | 87 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
91 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
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| RegAllocFast.cpp | 669 if (!MO.getSubReg()) {
675 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
706 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
744 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {
[all...] |
| MachineInstr.cpp | 72 if (SubIdx && getSubReg())
73 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
81 if (getSubReg()) {
82 Reg = TRI.getSubReg(Reg, getSubReg());
83 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
178 getSubReg() == Other.getSubReg();
217 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
267 OS << PrintReg(getReg(), TRI, getSubReg());
[all...] |
| RegisterCoalescer.cpp | 220 DstSub = MI->getOperand(0).getSubReg();
222 SrcSub = MI->getOperand(1).getSubReg();
225 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
228 SrcSub = MI->getOperand(2).getSubReg();
276 Dst = TRI.getSubReg(Dst, DstSub);
371 Dst = TRI.getSubReg(Dst, DstSub);
376 return TRI.getSubReg(DstReg, SrcSub) == Dst;
697 UseMI->getOperand(0).getSubReg())
763 if (DstOperand.getSubReg() && !DstOperand.isUndef())
[all...] |
| PeepholeOptimizer.cpp | 206 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
429 if (!MI->getOperand(0).getSubReg() &&
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| LiveDebugVariables.cpp | 185 locations[i].getSubReg() == LocMO.getSubReg())
567 if (UI.getOperand().getSubReg() || !UI->isCopy())
760 MO.setSubReg(locations[OldLocNo].getSubReg());
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 354 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
355 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
356 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
357 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
359 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
360 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
361 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
362 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
365 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
366 D1 = TRI->getSubReg(Reg, ARM::dsub_3)
[all...] |
| ARMMCInstLower.cpp | 74 assert(!MO.getSubReg() && "Subregs should be eliminated!");
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| Thumb2ITBlockPass.cpp | 113 assert(MI->getOperand(0).getSubReg() == 0 &&
114 MI->getOperand(1).getSubReg() == 0 &&
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 259 unsigned getSubReg() const {
767 SR = Start->getSubReg();
770 SR = End->getSubReg();
785 DistSR = End->getSubReg();
795 SubIB.addReg(End->getReg(), 0, End->getSubReg())
796 .addReg(Start->getReg(), 0, Start->getSubReg());
799 .addReg(Start->getReg(), 0, Start->getSubReg());
801 SubIB.addReg(End->getReg(), 0, End->getSubReg())
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 666 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
678 getOperand(0).getSubReg() == getOperand(1).getSubReg();
[all...] |
| MachineOperand.h | 264 unsigned getSubReg() const {
328 return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
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| /external/llvm/lib/Target/AArch64/ |
| AArch64MCInstLower.cpp | 94 assert(!MO.getSubReg() && "Subregs should be eliminated!");
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 725 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
727 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 342 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
357 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpeven))
359 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpodd))
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| MipsSEFrameLowering.cpp | 103 MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven));
104 MachineLocation SrcML1(RegInfo->getSubReg(Reg, Mips::sub_fpodd));
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| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 323 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
|
