| /external/openssl/crypto/sha/asm/ |
| sha1-mips.S | 39 lwl $8,3($5)
52 lwl $9,1*4+3($5)
76 lwl $10,2*4+3($5)
100 lwl $11,3*4+3($5)
124 lwl $12,4*4+3($5)
148 lwl $13,5*4+3($5)
172 lwl $14,6*4+3($5)
196 lwl $15,7*4+3($5)
220 lwl $16,8*4+3($5)
244 lwl $17,9*4+3($5
[all...] |
| sha256-mips.S | 49 lwl $8,3($5)
51 lwl $9,7($5)
103 lwl $10,11($5)
155 lwl $11,15($5)
207 lwl $12,19($5)
259 lwl $13,23($5)
311 lwl $14,27($5)
363 lwl $15,31($5)
415 lwl $16,35($5)
467 lwl $17,39($5
[all...] |
| sha1-mips.pl | 13 # to deploy lwl/lwr pair to load unaligned input. One could have
109 lwl @X[$j],$j*4+$MSB($inp)
287 lwl @X[0],$MSB($inp)
|
| /external/openssl/crypto/aes/asm/ |
| aes-mips.S | 41 lwl $12,2($1) # Te1[s1>>16]
42 lwl $13,2($2) # Te1[s2>>16]
43 lwl $14,2($24) # Te1[s3>>16]
44 lwl $15,2($25) # Te1[s0>>16]
62 lwl $16,1($1) # Te2[s2>>8]
63 lwl $17,1($2) # Te2[s3>>8]
64 lwl $18,1($24) # Te2[s0>>8]
65 lwl $19,1($25) # Te2[s1>>8]
83 lwl $20,0($1) # Te3[s3]
84 lwl $21,0($2) # Te3[s0
[all...] |
| aes-mips.pl | 18 # additional rotations. Rotations are implemented with lwl/lwr pairs,
142 lwl $t0,3($i0) # Te1[s1>>16]
143 lwl $t1,3($i1) # Te1[s2>>16]
144 lwl $t2,3($i2) # Te1[s3>>16]
145 lwl $t3,3($i3) # Te1[s0>>16]
163 lwl $t4,2($i0) # Te2[s2>>8]
164 lwl $t5,2($i1) # Te2[s3>>8]
165 lwl $t6,2($i2) # Te2[s0>>8]
166 lwl $t7,2($i3) # Te2[s1>>8]
184 lwl $t8,1($i0) # Te3[s3
[all...] |
| /bionic/libc/arch-mips/include/machine/ |
| asm.h | 68 #define LWLO lwl
79 #define LWHI lwl
|
| /development/ndk/platforms/android-9/arch-mips/include/machine/ |
| asm.h | 68 #define LWLO lwl
79 #define LWHI lwl
|
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/machine/ |
| asm.h | 68 #define LWLO lwl
79 #define LWHI lwl
|
| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/machine/ |
| asm.h | 68 #define LWLO lwl
79 #define LWHI lwl
|
| /bionic/libc/arch-mips/string/ |
| memcpy.S | 50 # define LWHI lwl /* high part is left in big-endian */
59 # define LWLO lwl /* low part is left in big-endian */
|
| /external/valgrind/main/none/tests/mips32/ |
| MIPS32int.stdout.exp | 278 LWL
279 lwl $t0, 0($t1) :: rt 0x1f000000
280 lwl $t0, 4($t1) :: rt 0x00000000
281 lwl $t0, 8($t1) :: rt 0x03000000
282 lwl $t0, 12($t1) :: rt 0xff000000
283 lwl $t0, 16($t1) :: rt 0x2f000000
284 lwl $t0, 20($t1) :: rt 0x2b000000
285 lwl $t0, 24($t1) :: rt 0x2b000000
286 lwl $t0, 28($t1) :: rt 0x2a000000
287 lwl $t0, 32($t1) :: rt 0x3e00000
[all...] |
| /external/qemu/target-mips/ |
| helper.h | 13 DEF_HELPER_3(lwl, tl, tl, tl, int)
|
| translate.c | [all...] |
| /external/v8/src/mips/ |
| disasm-mips.cc | 877 case LWL:
878 Format(instr, "lwl 'rt, 'imm16s('rs)");
|
| assembler-mips.h | 749 void lwl(Register rd, const MemOperand& rs);
[all...] |
| assembler-mips.cc | 1399 void Assembler::lwl(Register rd, const MemOperand& rs) { function in class:v8::Assembler
[all...] |
| code-stubs-mips.cc | [all...] |
| /external/webkit/Source/JavaScriptCore/assembler/ |
| MacroAssemblerMIPS.h | 538 lwl dest, address.offset(addrTemp)
541 lwl dest, address.offset+3(addrTemp)
547 m_assembler.lwl(dest, addrTempRegister, address.offset);
550 m_assembler.lwl(dest, addrTempRegister, address.offset + 3);
575 m_assembler.lwl(dest, addrTempRegister, 0);
578 m_assembler.lwl(dest, addrTempRegister, 3);
[all...] |
| MIPSAssembler.h | 427 void lwl(RegisterID rt, RegisterID rs, int offset) function in class:JSC::MIPSAssembler
|
| /external/v8/test/cctest/ |
| test-assembler-mips.cc | 837 // Test LWL, LWR, SWL and SWR instructions.
865 // Test all combinations of LWL and vAddr.
867 __ lwl(t0, MemOperand(a0, OFFSET_OF(T, mem_init)) );
871 __ lwl(t1, MemOperand(a0, OFFSET_OF(T, mem_init) + 1) );
875 __ lwl(t2, MemOperand(a0, OFFSET_OF(T, mem_init) + 2) );
879 __ lwl(t3, MemOperand(a0, OFFSET_OF(T, mem_init) + 3) );
[all...] |
