| /dalvik/vm/compiler/codegen/mips/Mips32/ |
| Gen.cpp | 148 opRegRegReg(cUnit, firstOp, rlResult.lowReg, rlResult.lowReg, rlSrc2.lowReg);
149 opRegRegReg(cUnit, secondOp, rlResult.highReg, rlResult.highReg, rlSrc2.highReg);
165 opRegRegReg(cUnit, firstOp, rlResult.lowReg, rlSrc1.lowReg, rlResult.lowReg);
166 opRegRegReg(cUnit, secondOp, rlResult.highReg, rlSrc1.highReg, rlResult.highReg);
180 opRegRegReg(cUnit, firstOp, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
181 opRegRegReg(cUnit, secondOp, rlResult.highReg, rlSrc1.highReg, rlSrc2.highReg);
|
| Factory.cpp | 234 static MipsLIR *opRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest,
267 ALOGE("Jit: bad case in opRegRegReg");
384 return opRegRegReg(cUnit, op, rDestSrc1, rDestSrc1, rSrc2);
|
| /dalvik/vm/compiler/codegen/arm/ |
| CodegenDriver.cpp | 736 opRegRegReg(cUnit, kOpSub, rlResult.lowReg,
757 opRegRegReg(cUnit, kOpOr, tReg, r2, r3);
867 opRegRegReg(cUnit, op, rlResult.lowReg,
872 opRegRegReg(cUnit, op, rlResult.lowReg,
[all...] |
| /dalvik/vm/compiler/codegen/arm/Thumb2/ |
| Gen.cpp | 133 opRegRegReg(cUnit, firstOp, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
134 opRegRegReg(cUnit, secondOp, rlResult.highReg, rlSrc1.highReg,
384 opRegRegReg(cUnit, kOpSub, rlTemp.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
|
| Factory.cpp | 492 static ArmLIR *opRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest,
772 opRegRegReg(cUnit, kOpAdd, regPtr, rBase, rIndex);
836 opRegRegReg(cUnit, kOpAdd, regPtr, rBase, rIndex);
[all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| CodegenDriver.cpp | 510 opRegRegReg(cUnit, kOpAdd, regPtr, rlArray.lowReg, rlIndex.lowReg);
582 opRegRegReg(cUnit, kOpAdd, tReg, rlArray.lowReg, rlIndex.lowReg);
813 opRegRegReg(cUnit, kOpOr, tReg, r_ARG2, r_ARG3);
928 opRegRegReg(cUnit, op, rlResult.lowReg,
933 opRegRegReg(cUnit, op, rlResult.lowReg,
[all...] |
| /dalvik/vm/compiler/codegen/arm/Thumb/ |
| Factory.cpp | 250 static ArmLIR *opRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest,
438 return opRegRegReg(cUnit, op, rDestSrc1, rDestSrc1, rSrc2);
|
