HomeSort by relevance Sort by last modified time
    Searched refs:prefetches (Results 1 - 7 of 7) sorted by null

  /external/oprofile/events/mips/r10000/
events 34 event:0x0e counters:1 um:zero minimum:500 name:STORES_OR_STORE_PREF_TO_CLEANEXCLUSIVE_SCACHE_BLOCKS : Stores or prefetches with store hint to CleanExclusive secondary cache blocks
36 event:0x0f counters:1 um:zero minimum:500 name:STORES_OR_STORE_PREF_TO_SHD_SCACHE_BLOCKS : Stores or prefetches with store hint to Shared secondary cache blocks
  /external/oprofile/events/i386/westmere/
unit_masks 135 0x10 prefetch_i_state L2 data prefetches in the I state (misses)
136 0x20 prefetch_s_state L2 data prefetches in the S state
137 0x40 prefetch_e_state L2 data prefetches in E state
138 0x80 prefetch_m_state L2 data prefetches in M state
139 0xf0 prefetch_mesi All L2 data prefetches
164 0xc0 prefetches All L2 prefetches
  /external/oprofile/events/mips/rm7000/
events 11 event:0x07 counters:0,1 um:zero minimum:500 name:BRANCH_PREFETCHES : Branch prefetches
  /external/oprofile/events/x86-64/family11h/
unit_masks 124 0x01 L2 fills (victims from L1 caches, TLB page table walks and data prefetches)
168 0x01 Cancelled prefetches
  /external/oprofile/events/x86-64/hammer/
unit_masks 113 0x01 L2 fills (victims from L1 caches, TLB page table walks and data prefetches)
162 0x01 Cancelled prefetches
  /external/oprofile/events/x86-64/family10/
unit_masks 132 0x01 L2 fills (victims from L1 caches, TLB page table walks and data prefetches)
181 0x01 Cancelled prefetches
  /external/oprofile/events/i386/nehalem/
events 27 event:0x0C counters:0,1,2,3 um:mem_store_retired minimum:6000 name:MEM_STORE_RETIRED : The event counts the number of retired stores that missed the DTLB. The DTLB miss is not counted if the store operation causes a fault. Does not count prefetches. Counts both primary and secondary misses to the TLB

Completed in 168 milliseconds