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  /external/llvm/lib/Target/ARM/
ARMRegisterInfo.cpp 21 ARMRegisterInfo::ARMRegisterInfo(const ARMBaseInstrInfo &tii,
23 : ARMBaseRegisterInfo(tii, sti) {
ARMRegisterInfo.h 28 ARMRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
ARMHazardRecognizer.h 31 const ARMBaseInstrInfo &TII;
40 const ARMBaseInstrInfo &tii,
44 ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), TII(tii),
Thumb2RegisterInfo.h 28 Thumb2RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
Thumb2RegisterInfo.cpp 27 Thumb2RegisterInfo::Thumb2RegisterInfo(const ARMBaseInstrInfo &tii,
29 : ARMBaseRegisterInfo(tii, sti) {
48 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
Thumb1RegisterInfo.h 28 Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
51 const ARMBaseInstrInfo &TII) const;
  /external/llvm/lib/Target/R600/
SIRegisterInfo.cpp 22 const TargetInstrInfo &tii)
23 : AMDGPURegisterInfo(tm, tii),
25 TII(tii)
R600RegisterInfo.h 28 const TargetInstrInfo &TII;
30 R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
SIRegisterInfo.h 28 const TargetInstrInfo &TII;
30 SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
AMDGPURegisterInfo.cpp 21 const TargetInstrInfo &tii)
24 TII(tii)
AMDGPURegisterInfo.h 33 const TargetInstrInfo &TII;
36 AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);
R600RegisterInfo.cpp 24 const TargetInstrInfo &tii)
25 : AMDGPURegisterInfo(tm, tii),
27 TII(tii)
58 const R600InstrInfo *RII = static_cast<const R600InstrInfo*>(&TII);
  /external/llvm/lib/Target/MBlaze/
MBlazeRegisterInfo.h 40 const TargetInstrInfo &TII;
43 const TargetInstrInfo &tii);
  /external/llvm/lib/Target/MSP430/
MSP430RegisterInfo.h 30 const TargetInstrInfo &TII;
36 MSP430RegisterInfo(MSP430TargetMachine &tm, const TargetInstrInfo &tii);
  /external/llvm/lib/Target/Sparc/
SparcRegisterInfo.h 30 const TargetInstrInfo &TII;
32 SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii);
SparcRegisterInfo.cpp 32 const TargetInstrInfo &tii)
33 : SparcGenRegisterInfo(SP::I7), Subtarget(st), TII(tii) {
84 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
86 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
  /external/llvm/lib/CodeGen/
Spiller.cpp 58 const TargetInstrInfo *tii; member in class:__anon11493::SpillerBase
68 tii = mf.getTarget().getInstrInfo();
136 tii->loadRegFromStackSlot(*mi->getParent(), miItr, newLI->reg, ss, trc,
149 tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr),newLI->reg,
  /external/llvm/lib/Target/AArch64/
AArch64RegisterInfo.h 29 const AArch64InstrInfo &TII;
32 AArch64RegisterInfo(const AArch64InstrInfo &tii,
AArch64RegisterInfo.cpp 32 AArch64RegisterInfo::AArch64RegisterInfo(const AArch64InstrInfo &tii,
34 : AArch64GenRegisterInfo(AArch64::X30), TII(tii) {
132 TII.getAddressConstraints(MI, OffsetScale, MinOffset, MaxOffset);
141 emitRegUpdate(MBB, MBBI, MBBI->getDebugLoc(), TII,
  /external/llvm/lib/Target/Hexagon/
HexagonRegisterInfo.h 47 const HexagonInstrInfo &TII;
49 HexagonRegisterInfo(HexagonSubtarget &st, const HexagonInstrInfo &tii);
  /external/llvm/lib/Target/NVPTX/
NVPTXRegisterInfo.h 39 NVPTXRegisterInfo(const TargetInstrInfo &tii,
  /external/llvm/lib/Target/XCore/
XCoreRegisterInfo.h 28 const TargetInstrInfo &TII;
43 XCoreRegisterInfo(const TargetInstrInfo &tii);
  /external/llvm/include/llvm/CodeGen/
TargetSchedule.h 38 const TargetInstrInfo *TII;
44 TargetSchedModel(): STI(0), TII(0) {}
52 const TargetInstrInfo *tii);
58 const TargetInstrInfo *getInstrInfo() const { return TII; }
  /external/llvm/lib/Target/PowerPC/
PPCRegisterInfo.h 32 const TargetInstrInfo &TII;
34 PPCRegisterInfo(const PPCSubtarget &SubTarget, const TargetInstrInfo &tii);
  /external/llvm/lib/Target/X86/
X86RegisterInfo.h 30 const TargetInstrInfo &TII;
59 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);

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