| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 74 v32i8 = 23, // 32 x i8 enumerator in enum:llvm::MVT::SimpleValueType
219 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 ||
272 case v32i8:
306 case v32i8:
393 case v32i8:
495 if (NumElements == 32) return MVT::v32i8;
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 78 DecodePALIGNRMask(MVT::v32i8,
160 DecodeUNPCKHMask(MVT::v32i8, ShuffleMask);
233 DecodeUNPCKLMask(MVT::v32i8, ShuffleMask);
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 141 case MVT::v32i8: return "v32i8";
204 case MVT::v32i8: return VectorType::get(Type::getInt8Ty(Context), 32);
|
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 302 { ISD::SETCC, MVT::v32i8, 4 },
309 { ISD::SETCC, MVT::v32i8, 1 },
|
| X86ISelLowering.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 82 case MVT::v32i8: return "MVT::v32i8";
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 39 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
|
