| /external/clang/test/CodeGen/ |
| mips-vector-arg.c | 9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
24 extern test_v4i32_2(v4i32, int, v4i32);
25 void test_v4i32(v4i32 a1, int a2, v4i32 a3) {
|
| mips-vector-return.c | 9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
28 v4i32 test_v4i32(int a) {
29 return (v4i32){0, a, 0, 0};
|
| compound-literal.c | 6 typedef int v4i32 __attribute((vector_size(16))); typedef
7 v4i32 *y = &(v4i32){1,2,3,4};
|
| x86_32-arguments-darwin.c | 224 typedef int v4i32 __attribute__((__vector_size__(16))); typedef
228 v4i32 f55(v4i32 arg) { return arg+arg; }
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 207 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
208 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
211 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
212 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
223 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
224 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
247 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
248 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
436 { ISD::VECTOR_SHUFFLE, MVT::v4i32, 2 },
|
| ARMISelLowering.cpp | 159 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
467 addQRTypeForNEON(MVT::v4i32);
546 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
571 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
599 // It is legal to extload from v4i8 to v4i16 or v4i32.
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 209 // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle,
211 if (ISD == ISD::MUL && LT.second == MVT::v4i32 && ST->hasSSE2() &&
247 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
248 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
249 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
290 { ISD::SETCC, MVT::v4i32, 1 },
|
| X86ISelLowering.cpp | [all...] |
| X86FastISel.cpp | 271 case MVT::v4i32:
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 84 v4i32 = 33, // 4 x i32 enumerator in enum:llvm::MVT::SimpleValueType
212 SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 ||
282 case v4i32:
326 case v4i32:
389 case v4i32:
509 if (NumElements == 4) return MVT::v4i32;
|
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 34 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
43 setOperationAction(ISD::ADD, MVT::v4i32, Expand);
44 setOperationAction(ISD::AND, MVT::v4i32, Expand);
45 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand);
46 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand);
47 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand);
48 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand);
49 setOperationAction(ISD::UDIV, MVT::v4i32, Expand);
50 setOperationAction(ISD::UREM, MVT::v4i32, Expand);
51 setOperationAction(ISD::SETCC, MVT::v4i32, Expand)
[all...] |
| AMDILISelLowering.cpp | 55 (int)MVT::v4i32,
80 (int)MVT::v4i32,
411 INTTY = MVT::v4i32;
556 INTTY = MVT::v4i32;
573 INTTY = MVT::v4i32;
|
| AMDGPUISelLowering.cpp | 55 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
61 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
|
| SIISelLowering.cpp | 50 addRegisterClass(MVT::v4i32, &AMDGPU::VReg_128RegClass);
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 90 DecodePSHUFMask(MVT::v4i32, MI->getOperand(MI->getNumOperands()-1).getImm(),
188 DecodeUNPCKHMask(MVT::v4i32, ShuffleMask);
261 DecodeUNPCKLMask(MVT::v4i32, ShuffleMask);
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 151 case MVT::v4i32: return "v4i32";
214 case MVT::v4i32: return VectorType::get(Type::getInt32Ty(Context), 4);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 333 // We promote all non-typed operations to v4i32.
335 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
337 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
339 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
341 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
343 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
345 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
401 setOperationAction(ISD::AND , MVT::v4i32, Legal);
402 setOperationAction(ISD::OR , MVT::v4i32, Legal);
403 setOperationAction(ISD::XOR , MVT::v4i32, Legal)
[all...] |
| PPCISelDAGToDAG.cpp | 638 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
649 else if (VecVT == MVT::v4i32)
663 else if (VecVT == MVT::v4i32)
676 else if (VecVT == MVT::v4i32)
701 // types (v16i8, v8i16, v4i32, and v4f32).
708 case MVT::v4i32:
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 92 case MVT::v4i32: return "MVT::v4i32";
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 60 case MVT::v4i32:
[all...] |
