/external/llvm/lib/Target/X86/ |
X86TargetTransformInfo.cpp | 179 { ISD::SUB, MVT::v4i64, 4 }, 180 { ISD::ADD, MVT::v4i64, 4 }, 181 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 183 // Because we believe v4i64 to be a legal type, we must also include the 186 { ISD::MUL, MVT::v4i64, 18 }, 199 // A v2i64/v4i64 and multiply is custom lowered as a series of long 202 { ISD::MUL, MVT::v4i64, 9 }, 247 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 248 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 249 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 } [all...] |
X86ISelLowering.cpp | [all...] |
/external/llvm/include/llvm/CodeGen/ |
ValueTypes.h | 89 v4i64 = 38, // 4 x i64 enumerator in enum:llvm::MVT::SimpleValueType 220 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64); 287 case v4i64: 327 case v4i64: 396 case v4i64: 516 if (NumElements == 4) return MVT::v4i64;
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/external/llvm/lib/Target/X86/InstPrinter/ |
X86InstComments.cpp | 214 DecodeUNPCKHMask(MVT::v4i64, ShuffleMask); 287 DecodeUNPCKLMask(MVT::v4i64, ShuffleMask); 442 // For instruction comments purpose, assume the 256-bit vector is v4i64. 443 DecodeVPERM2X128Mask(MVT::v4i64,
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/external/llvm/lib/IR/ |
ValueTypes.cpp | 156 case MVT::v4i64: return "v4i64"; 219 case MVT::v4i64: return VectorType::get(Type::getInt64Ty(Context), 4);
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/external/llvm/lib/Target/ARM/ |
ARMTargetTransformInfo.cpp | 211 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, 395 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
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ARMISelDAGToDAG.cpp | [all...] |
ARMISelLowering.cpp | [all...] |
/external/llvm/utils/TableGen/ |
CodeGenTarget.cpp | 97 case MVT::v4i64: return "MVT::v4i64";
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