| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 99 v8f32 = 44, // 8 x f32 enumerator in enum:llvm::MVT::SimpleValueType
218 return (SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 ||
293 case v8f32:
321 case v8f32:
397 case v8f32:
526 if (NumElements == 8) return MVT::v8f32;
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 238 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
239 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
240 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
241 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
267 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
268 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 },
|
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 251 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
253 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
255 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
297 { ISD::SETCC, MVT::v8f32, 1 },
|
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 326 DecodeSHUFPMask(MVT::v8f32, MI->getOperand(MI->getNumOperands()-1).getImm(),
364 DecodeUNPCKLMask(MVT::v8f32, ShuffleMask);
400 DecodeUNPCKHMask(MVT::v8f32, ShuffleMask);
416 DecodePSHUFMask(MVT::v8f32, MI->getOperand(MI->getNumOperands()-1).getImm(),
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 162 case MVT::v8f32: return "v8f32";
225 case MVT::v8f32: return VectorType::get(Type::getFloatTy(Context), 8);
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 54 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
62 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 103 case MVT::v8f32: return "MVT::v8f32";
|
