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Searched
defs:DAG
(Results
26 - 31
of
31
) sorted by null
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/external/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp
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//===-- SelectionDAGBuilder.cpp - Selection-
DAG
building ------------------===//
74
// Limit the width of
DAG
chains. This is important in general to prevent
75
// prevent
DAG
-based analysis from blowing up. For example, alias analysis and
78
// future analyses are likely to have the same behavior. Limiting
DAG
width is
90
static SDValue getCopyFromPartsVector(SelectionDAG &
DAG
, DebugLoc DL,
99
static SDValue getCopyFromParts(SelectionDAG &
DAG
, DebugLoc DL,
105
return getCopyFromPartsVector(
DAG
, DL, Parts, NumParts,
109
const TargetLowering &TLI =
DAG
.getTargetLoweringInfo();
123
ValueVT : EVT::getIntegerVT(*
DAG
.getContext(), RoundBits);
126
EVT HalfVT = EVT::getIntegerVT(*
DAG
.getContext(), RoundBits/2)
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DAGCombiner.cpp
1
//===-- DAGCombiner.cpp - Implement a
DAG
node combiner -------------------===//
10
// This pass combines
dag
nodes to form fewer, simpler
DAG
nodes. It can be run
11
// both before and after the
DAG
is legalized.
41
STATISTIC(NodesCombined , "Number of
dag
nodes combined");
59
SelectionDAG &
DAG
;
86
// AA - Used for
DAG
load/store alias analysis.
163
/// target-specific
DAG
combines.
166
// Visitation implementation - Implement
dag
node combining for different
318
:
DAG
(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes)
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/external/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp
1
//===-- PPCISelLowering.cpp - PPC
DAG
Lowering Implementation -------------===//
467
// We have target-specific
dag
combine patterns for the following nodes:
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/external/llvm/lib/Target/ARM/
ARMISelLowering.cpp
1
//===-- ARMISelLowering.cpp - ARM
DAG
Lowering Implementation -------------===//
11
// selection
DAG
.
482
// In another words, find a way when "copysign" appears in
DAG
with vector
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/external/llvm/lib/Target/X86/
X86ISelLowering.cpp
1
//===-- X86ISelLowering.cpp - X86
DAG
Lowering Implementation -------------===//
11
// selection
DAG
.
58
static SDValue getMOVL(SelectionDAG &
DAG
, DebugLoc dl, EVT VT, SDValue V1,
61
/// Generate a
DAG
to grab 128-bits from a vector > 128 bits. This
67
SelectionDAG &
DAG
, DebugLoc dl) {
72
EVT ResultVT = EVT::getVectorVT(*
DAG
.getContext(), ElVT,
77
return
DAG
.getUNDEF(ResultVT);
90
return
DAG
.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
93
SDValue VecIdx =
DAG
.getIntPtrConstant(NormalizedIdxVal);
94
SDValue Result =
DAG
.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec
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/prebuilts/tools/common/eclipse/
org.eclipse.ui.workbench.texteditor_3.6.1.r361_v20100714-0800.jar
Completed in 537 milliseconds
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