| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/linux/ |
| serial_reg.h | 23 #define UART_IER 1 /* Out: Interrupt Enable Register */
24 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
25 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
27 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
33 #define UART_IIR 2 /* In: Interrupt ID Register */
35 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
36 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
38 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
39 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
116 #define UART_LSR_BI 0x10 /* Break interrupt indicator *
[all...] |
| pmu.h | 29 #define PMU_SET_INTR_MASK 0x70 /* set PMU interrupt mask */
30 #define PMU_INT_ACK 0x78 /* read interrupt bits */
55 /* Bits in PMU interrupt and interrupt mask bytes */
61 #define PMU_INT_TICK 0x80 /* 1-second tick interrupt */
63 /* Other bits in PMU interrupt valid when PMU_INT_ADB is set */
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/linux/ |
| serial_reg.h | 23 #define UART_IER 1 /* Out: Interrupt Enable Register */
24 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
25 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
27 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
33 #define UART_IIR 2 /* In: Interrupt ID Register */
35 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
36 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
38 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
39 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
116 #define UART_LSR_BI 0x10 /* Break interrupt indicator *
[all...] |
| pmu.h | 29 #define PMU_SET_INTR_MASK 0x70 /* set PMU interrupt mask */
30 #define PMU_INT_ACK 0x78 /* read interrupt bits */
55 /* Bits in PMU interrupt and interrupt mask bytes */
61 #define PMU_INT_TICK 0x80 /* 1-second tick interrupt */
63 /* Other bits in PMU interrupt valid when PMU_INT_ADB is set */
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/linux/ |
| serial_reg.h | 23 #define UART_IER 1 /* Out: Interrupt Enable Register */
24 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
25 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
27 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
33 #define UART_IIR 2 /* In: Interrupt ID Register */
35 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
36 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
38 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
39 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
116 #define UART_LSR_BI 0x10 /* Break interrupt indicator *
[all...] |
| pmu.h | 29 #define PMU_SET_INTR_MASK 0x70 /* set PMU interrupt mask */
30 #define PMU_INT_ACK 0x78 /* read interrupt bits */
55 /* Bits in PMU interrupt and interrupt mask bytes */
61 #define PMU_INT_TICK 0x80 /* 1-second tick interrupt */
63 /* Other bits in PMU interrupt valid when PMU_INT_ADB is set */
|
| /dalvik/tests/050-sync-test/src/ |
| Main.java | 27 System.out.println("INTERRUPT!");
44 System.out.println("INTERRUPT!");
56 System.out.println("INTERRUPT!");
166 mOther.interrupt();
|
| /development/samples/USB/MissileLauncher/ |
| _index.html | 9 <li>Receiving packets on an interrupt endpoint using a thread that calls
|
| /external/kernel-headers/original/asm-arm/ |
| dma.h | 58 * Some architectures may need to do allocate an interrupt
64 * Some architectures may need to do free an interrupt
71 * enabling an interrupt and setting the DMA registers.
78 * disabling an interrupt or whatever.
|
| /external/kernel-headers/original/asm-x86/ |
| irq_32.h | 48 /* Interrupt vector management */
|
| /external/kernel-headers/original/linux/ |
| kxtf9.h | 63 /* INTERRUPT CONTROL REGISTER 1 BITS */
64 #define IEN 0x20 /* interrupt enable */
65 #define IEA 0x10 /* interrupt polarity */
66 #define IEL 0x08 /* interrupt response */
|
| preempt.h | 6 * preempt_count (used for kernel preemption, interrupt count, etc.)
|
| serio.h | 18 #include <linux/interrupt.h>
35 spinlock_t lock; /* protects critical sections from port's interrupt handler */
45 struct serio_driver *drv; /* accessed from interrupt, must be protected by serio->lock and serio->sem */
63 irqreturn_t (*interrupt)(struct serio *, unsigned char, member in struct:serio_driver
138 * driver code from port's interrupt handler
172 * bit masks for use in "interrupt" flags (3rd argument)
|
| /external/oprofile/module/ |
| oprofile.h | 92 * A interrupt handler must implement these routines.
93 * When an interrupt arrives, it must eventually call
97 /* initialise the interrupt handler on module load.
140 /* used by interrupt handlers if the underlined harware doesn't support
|
| /external/qemu/android/config/linux-x86/asm/ |
| kvm.h | 23 /* Architectural interrupt line count. */
37 __u8 irr; /* interrupt request register */
38 __u8 imr; /* interrupt mask register */
39 __u8 isr; /* interrupt service register */
|
| /external/qemu/android/config/linux-x86_64/asm/ |
| kvm.h | 23 /* Architectural interrupt line count. */
37 __u8 irr; /* interrupt request register */
38 __u8 imr; /* interrupt mask register */
39 __u8 isr; /* interrupt service register */
|
| /external/qemu/hw/ |
| arm-misc.h | 14 /* The CPU is also modeled as an interrupt controller. */
|
| arm_pic.c | 2 * Generic ARM Programmable Interrupt Controller support.
|
| arm_gic.c | 2 * ARM Generic/Distributed Interrupt Controller
10 /* This file contains implementation code for the RealView EB interrupt
11 controller, MPCore distributed interrupt controller and ARMv7-M
12 Nested Vectored Interrupt Controller. */
102 /* Update interrupt status after enabled or pending bits have been changed. */
158 /* The first external input line is internal interrupt 32. */
264 /* Interrupt Set/Clear Enable. */
279 /* Interrupt Set/Clear Pending. */
295 /* Interrupt Active. */
307 /* Interrupt Priority. *
[all...] |
| /external/valgrind/main/gdbserver_tests/ |
| mcinfcallRU.stdinB.gdb | 6 # We will interrupt in a few seconds (be sure the main task is ready).
|
| /external/webkit/Source/WebCore/manual-tests/ |
| invalid-mouse-event.html | 8 <li>If Safari doesn't crash in a while, interrupt the test by pressing Cmd+W.</li>
|
| /external/kernel-headers/original/asm-mips/ |
| jazz.h | 146 * JAZZ timer registers and interrupt no.
147 * Note that the hardware timer interrupt is actually on
182 * JAZZ interrupt control registers
188 * JAZZ Interrupt Level definitions
191 * we remap the Jazz interrupts to the usual ISA style interrupt numbers.
250 #define JAZZ_R4030_IRQ_ENABLE 0xE00000E8 /* Internal Interrupt Enable */
252 #define JAZZ_R4030_IRQ_SOURCE 0xE0000200 /* Interrupt Source Register */
258 #define JAZZ_EISA_IRQ_ACK 0xE0000238 /* EISA interrupt acknowledge */
|
| /external/robolectric/src/test/java/com/xtremelabs/robolectric/bytecode/ |
| ClassCacheTest.java | 42 locker.interrupt();
81 locker.interrupt();
|
| /frameworks/base/core/java/android/os/ |
| SystemClock.java | 69 * be interrupted with {@link Thread#interrupt Thread.interrupt()}, and
75 * you do not use {@link Thread#interrupt Thread.interrupt()}, as it will
102 * {@link InterruptedException}; {@link Thread#interrupt()} events are
124 // Important: we don't want to quietly eat an interrupt() event,
125 // so we make sure to re-interrupt the thread so that the next
127 Thread.currentThread().interrupt();
|
| /external/grub/netboot/ |
| epic100.h | 17 INTSTAT= 4, /* Interrupt Status */
18 INTMASK= 8, /* Interrupt Mask */
53 /* Interrupt register bits. NI means No Interrupt generated */
61 #define INTR_INTR_ACTIVE (0x00010000) /* Interrupt active. NI */
184 #define TD_IAF (0x0004) /* Generate Interrupt after tx */
|
