| /external/libvpx/libvpx/vpx_scale/arm/neon/ |
| vp8_vpxyv12_copyframe_func_neon.asm | 31 ldr r8, [r0, #yv12_buffer_config_u_buffer] ;srcptr1
32 ldr r9, [r1, #yv12_buffer_config_u_buffer] ;srcptr1
33 ldr r10, [r0, #yv12_buffer_config_v_buffer] ;srcptr1
34 ldr r11, [r1, #yv12_buffer_config_v_buffer] ;srcptr1
36 ldr r4, [r0, #yv12_buffer_config_y_height]
37 ldr r5, [r0, #yv12_buffer_config_y_width]
38 ldr r6, [r0, #yv12_buffer_config_y_stride]
39 ldr r7, [r1, #yv12_buffer_config_y_stride]
40 ldr r2, [r0, #yv12_buffer_config_y_buffer] ;srcptr1
41 ldr r3, [r1, #yv12_buffer_config_y_buffer] ;dstptr
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| fast-isel-frameaddr.ll | 38 ; DARWIN-ARM: ldr r0, [r0]
44 ; DARWIN-THUMB2: ldr r0, [r0]
50 ; LINUX-ARM: ldr r0, [r0]
56 ; LINUX-THUMB2: ldr r0, [r0]
68 ; DARWIN-ARM: ldr r0, [r0]
69 ; DARWIN-ARM: ldr r0, [r0]
70 ; DARWIN-ARM: ldr r0, [r0]
76 ; DARWIN-THUMB2: ldr r0, [r0]
77 ; DARWIN-THUMB2: ldr r0, [r0]
78 ; DARWIN-THUMB2: ldr r0, [r0
[all...] |
| ldr_post.ll | 5 ; CHECK: ldr {{.*, \[.*]}}, -r2
6 ; CHECK-NOT: ldr
17 ; CHECK: ldr {{.*, \[.*\]}}, #-16
18 ; CHECK-NOT: ldr
|
| ldr_pre.ll | 5 ; CHECK: ldr {{.*!}}
6 ; CHECK-NOT: ldr
15 ; CHECK: ldr {{.*!}}
16 ; CHECK-NOT: ldr
|
| ldr.ll | 5 ; CHECK: ldr r0
13 ; CHECK: ldr r0
23 ; CHECK: ldr r0
33 ; CHECK: ldr r0
43 ; CHECK: ldr r0
53 ; CHECK: ldr r0{{.*}}lsl{{.*}}
64 ; CHECK: ldr r0{{.*}}lsr{{.*}}
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| hex-immediates.txt | 2 # CHECK: ldr r4, [pc, #0x20]
|
| invalid-LDRrs-arm.txt | 3 # LDR (register) has encoding Inst{4} = 0.
|
| thumb-printf.txt | 8 # CHECK-NEXT: ldr r5, [r3], #4
10 # CHECK-NEXT: ldr r3, [pc, #52]
12 # CHECK-NEXT: ldr r0, [r3]
13 # CHECK-NEXT: ldr r4, [r0]
14 # CHECK-NEXT: ldr r0, [pc, #48]
16 # CHECK-NEXT: ldr r0, [r0]
17 # CHECK-NEXT: ldr r0, [r0]
20 # CHECK-NEXT: ldr r1, [pc, #40]
22 # CHECK-NEXT: ldr r1, [r1]
27 # CHECK-NEXT: ldr r3, [sp
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| armVCM4P10_Average_4x_Align_unsafe_s.s | 75 LDR r0x80808080, =0x80808080
117 LDR r0x80808080, =0x80808080
120 LDR Temp1, [pPred0, #4]
142 LDR Temp1, [pPred0, #4]
144 LDR iPredB0, [pPred1]
145 LDR iPredB1, [pPred1, iPredStep1]
146 LDR Temp2, [pPred0, #4]
172 LDR r0x80808080, =0x80808080
175 LDR Temp1, [pPred0, #4]
177 LDR iPredB0, [pPred1
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_Average_4x_Align_unsafe_s.s | 75 LDR r0x80808080, =0x80808080
117 LDR r0x80808080, =0x80808080
120 LDR Temp1, [pPred0, #4]
142 LDR Temp1, [pPred0, #4]
144 LDR iPredB0, [pPred1]
145 LDR iPredB1, [pPred1, iPredStep1]
146 LDR Temp2, [pPred0, #4]
172 LDR r0x80808080, =0x80808080
175 LDR Temp1, [pPred0, #4]
177 LDR iPredB0, [pPred1
[all...] |
| /dalvik/vm/compiler/template/armv5te/ |
| TEMPLATE_INVOKE_METHOD_NO_OPT.S | 9 ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd
19 ldr r9, [r0, #offMethod_clazz] @ r9<- method->clazz
20 ldr r10, [r0, #offMethod_accessFlags] @ r10<- methodToCall->accessFlags
23 ldr rPC, [r0, #offMethod_insns] @ rPC<- methodToCall->insns
39 ldr r10, .LdvmJitToInterpTraceSelectNoChain
40 ldr r3, [r9, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex
51 ldr ip, .LdvmFastMethodTraceEnter
|
| TEMPLATE_INVOKE_METHOD_NATIVE.S | 3 ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd
20 ldr r8, [r0, #offMethod_nativeFunc] @ r8<- method->nativeFunc
28 ldr r9, [rSELF, #offThread_jniLocal_topCookie]@r9<-thread->localRef->...
47 ldr ip, .LdvmFastMethodTraceEnter
57 ldr ip, .LdvmFastNativeMethodTraceExit
62 ldr r2, [r10, #offStackSaveArea_returnAddr] @ r2 = chaining cell ret
63 ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved->top
64 ldr r1, [rSELF, #offThread_exception] @ check for exception
68 ldr r0, [rFP, #(offStackSaveArea_currentPc - sizeofStackSaveArea)]
78 ldr r1, .LdvmJitToInterpTraceSelectNoChain @ defined in footer.
[all...] |
| /dalvik/vm/mterp/armv5te/ |
| OP_IPUT_OBJECT.S | 14 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
16 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
18 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
21 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
23 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
38 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
42 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
|
| OP_SPUT_OBJECT.S | 12 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
14 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
15 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
22 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
23 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
42 ldr r2, [rSELF, #offThread_method] @ r2<- current method
47 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
|
| OP_INVOKE_DIRECT.S | 16 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
18 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
20 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
40 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
41 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
|
| OP_SGET_WIDE.S | 10 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
12 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
13 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
39 ldr r2, [rSELF, #offThread_method] @ r2<- current method
44 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
|
| OP_SPUT.S | 12 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
14 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
15 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
35 ldr r2, [rSELF, #offThread_method] @ r2<- current method
40 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
|
| /external/llvm/test/CodeGen/AArch64/ |
| global-alignment.ll | 12 ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load.
16 ; CHECK: ldr x0, [x[[ADDR]]]
25 ; However, var64 *is* properly aligned and emitting an adrp/add/ldr would be
30 ; CHECK: ldr x0, [x[[HIBITS]], #:lo12:var64]
40 ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load.
44 ; CHECK: ldr x0, [x[[HIBITS]], #:lo12:var32_align64]
60 ; CHECK: ldr x0, [x[[ADDR]]]
|
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-ldr.ll | 6 ; CHECK: ldr r0, [r0]
14 ; CHECK: ldr.w r0, [r0, #4092]
24 ; CHECK: ldr r0, [r0, r1]
33 ; CHECK: ldr r0, [r0, #-128]
43 ; CHECK: ldr r0, [r0, r1]
53 ; CHECK: ldr.w r0, [r0, r1, lsl #2]
65 ; CHECK: ldr r0, [r0, r1]
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| armVCM4P10_InterpolateLuma_Align_unsafe_s.S | 85 LDR r7,[r0],r1
91 LDR r10,[r0,#4]
92 LDR r7,[r0],r1
100 LDR r10,[r0,#4]
101 LDR r7,[r0],r1
109 LDR r10,[r0,#4]
110 LDR r7,[r0],r1
|
| /frameworks/native/opengl/libagl/ |
| iterators.S | 52 ldr r4, [sp, #4*6]
61 ldr r5, [r0, #0]
62 ldr r12, [r0, #4]
64 ldr r5, [r0, #8]
66 ldr r12, [r0, #12]
70 ldr r3, [r0, #16] // m_x0
71 ldr r4, [r0, #20] // m_x1
|
| /external/openssl/crypto/sha/asm/ |
| sha256-armv4.S | 38 ldr r3,[r1],#4
49 ldr r12,[r14],#4 @ *K256++
72 ldr r1,[sp,#2*4] @ from BODY_16_xx
82 ldr r3,[r1],#4
93 ldr r12,[r14],#4 @ *K256++
116 ldr r1,[sp,#3*4] @ from BODY_16_xx
126 ldr r3,[r1],#4
137 ldr r12,[r14],#4 @ *K256++
160 ldr r1,[sp,#4*4] @ from BODY_16_xx
170 ldr r3,[r1],#
[all...] |
| /external/libvpx/libvpx/vp8/common/arm/armv6/ |
| loopfilter_v6.asm | 67 ldr count, [sp, #40] ; count for 8-in-parallel
68 ldr r6, [sp, #36] ; load thresh address
71 ldr r9, [src], pstep ; p3
73 ldr r10, [src], pstep ; p2
75 ldr r11, [src], pstep ; p1
88 ldr r12, [src], pstep ; p0
102 ldr r9, [src], pstep ; q0
103 ldr r10, [src], pstep ; q1
114 ldr r7, c0x7F7F7F7F
116 ldr r11, [src], pstep ; q
[all...] |
| /frameworks/av/media/libstagefright/codecs/mp3dec/src/asm/ |
| pvmp3_dct_9_arm.s | 55 ldr r2, [r0, #0x20]
56 ldr r3, [r0]
57 ldr r12,[r0, #4]
60 ldr r3,[r0, #0x1c]
61 ldr r4,[r0, #0x18]
63 ldr r5,[r0,#8]
67 ldr r5,[r0, #0x14]
68 ldr r7,[r0, #0xc]
69 ldr r9,[r0, #0x10]
80 ldr r11,|cos_2pi_9
[all...] |
| pvmp3_dct_9_gcc.s | 44 ldr r2, [r0, #0x20]
45 ldr r3, [r0, #0]
46 ldr r12,[r0, #4]
49 ldr r3,[r0, #0x1c]
50 ldr r4,[r0, #0x18]
52 ldr r5,[r0,#8]
56 ldr r5,[r0, #0x14]
57 ldr r7,[r0, #0xc]
58 ldr r9,[r0, #0x10]
69 ldr r11,cos_2pi_
[all...] |
