| /dalvik/vm/mterp/armv5te/ |
| OP_IPUT_WIDE.S | 9 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
11 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
13 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
16 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
18 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
34 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
|
| OP_SGET.S | 12 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
14 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
15 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
19 ldr r1, [r0, #offStaticField_value] @ r1<- field value
34 ldr r2, [rSELF, #offThread_method] @ r2<- current method
39 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
|
| OP_CHECK_CAST.S | 15 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex
17 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses
19 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class
20 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
46 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class)
59 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
62 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
67 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
|
| /dalvik/vm/mterp/armv6t2/ |
| OP_IGET_WIDE.S | 11 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
13 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
15 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
18 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
20 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
34 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
|
| OP_IPUT.S | 14 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
16 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
18 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
21 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
23 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
37 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
|
| OP_IPUT_WIDE.S | 8 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
12 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
15 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
17 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
32 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
|
| /external/libvpx/libvpx/vp8/common/arm/armv6/ |
| dc_only_idct_add_v6.asm | 27 ldr r12, c0x0000FFFF
28 ldr r4, [r1], r2
30 ldr r6, [r1], r2
33 ldr r12, [sp, #16] ; dst stride
45 ldr r4, [r1], r2
47 ldr r6, [r1]
|
| dequant_idct_v6.asm | 23 ldr r4, [r0] ;input
24 ldr r5, [r1], #4 ;dq
35 ldr r4, [r0, #4] ;input
36 ldr r5, [r1], #4 ;dq
58 ldr r3, cospi8sqrt2minus1
59 ldr r4, sinpi8sqrt2
60 ldr r6, [r0, #8]
63 ldr r12, [r0, #24]
64 ldr r14, [r0, #16]
78 ldr r11, [r0], #
[all...] |
| vp8_variance_halfpixvar16x16_hv_armv6.asm | 33 ldr r10, c80808080
40 ldr r4, [r0, #0] ; load source pixels a, row N
41 ldr r6, [r0, #1] ; load source pixels b, row N
42 ldr r5, [r9, #0] ; load source pixels c, row N+1
43 ldr r7, [r9, #1] ; load source pixels d, row N+1
56 ldr r5, [r2, #0] ; load 4 ref pixels
80 ldr r4, [r0, #4] ; load source pixels a, row N
81 ldr r6, [r0, #5] ; load source pixels b, row N
82 ldr r5, [r9, #4] ; load source pixels c, row N+1
86 ldr r7, [r9, #5] ; load source pixels d, row N+
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| inline-asm-modifiers.ll | 14 call void asm sideeffect "ldr x0, [x0, ${0:L}]", "S,~{x0}"(i32* @var_got)
17 call void asm sideeffect "ldr x0, [x0, ${0:L}]", "S,~{x0}"(i32* @var_tlsie)
20 ; CHECK: ldr x0, [x0, #:got_lo12:var_got]
23 ; CHECK: ldr x0, [x0, #:gottprel_lo12:var_tlsie]
95 call float asm sideeffect "ldr ${0:b}, [sp]", "=w"()
96 call float asm sideeffect "ldr ${0:h}, [sp]", "=w"()
97 call float asm sideeffect "ldr ${0:s}, [sp]", "=w"()
98 call float asm sideeffect "ldr ${0:d}, [sp]", "=w"()
99 call float asm sideeffect "ldr ${0:q}, [sp]", "=w"()
100 ; CHECK: ldr b0, [sp
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/source/arm11_asm/ |
| h264bsd_interpolate_hor_quarter.s | 95 LDR partW, [sp,#0x220] ;// partWidth
98 LDR width, [sp,#0x218] ;// width
104 LDR partH, [sp,#0x224] ;// partHeight
106 LDR height, [sp,#0x21c] ;// height
112 LDR partH, [sp,#0x224] ;// partHeight
113 LDR height, [sp,#0x21c] ;// height
114 LDR partW, [sp,#0x220] ;// partWidth
119 LDR width, [sp,#0x218] ;// width
132 LDR x0 ,[sp,#0x1ec] ;// x0
133 LDR y0 ,[sp,#0x1f0] ;// y
[all...] |
| /external/libvpx/libvpx/vpx_scale/arm/neon/ |
| vp8_vpxyv12_copy_y_neon.asm | 27 ldr r4, [r0, #yv12_buffer_config_y_height]
28 ldr r5, [r0, #yv12_buffer_config_y_width]
29 ldr r6, [r0, #yv12_buffer_config_y_stride]
30 ldr r7, [r1, #yv12_buffer_config_y_stride]
31 ldr r2, [r0, #yv12_buffer_config_y_buffer] ;srcptr1
32 ldr r3, [r1, #yv12_buffer_config_y_buffer] ;dstptr1
77 ldr r2, [r0, #yv12_buffer_config_y_buffer] ;srcptr1
78 ldr r3, [r1, #yv12_buffer_config_y_buffer] ;dstptr1
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| Dot_p_opt.s | 39 LDR r6, [r0], #4
40 LDR r7, [r1], #4
41 LDR r8, [r0], #4
43 LDR r9, [r1], #4
46 LDR r6, [r0], #4
49 LDR r7, [r1], #4
51 LDR r8, [r0], #4
54 LDR r9, [r1], #4
|
| /external/libvpx/libvpx/vp8/encoder/arm/armv6/ |
| vp8_fast_quantize_b_armv6.asm | 27 ldr r3, [r0, #vp8_block_coeff] ; coeff
28 ldr r4, [r0, #vp8_block_quant_fast] ; quant_fast
29 ldr r5, [r0, #vp8_block_round] ; round
30 ldr r6, [r1, #vp8_blockd_qcoeff] ; qcoeff
31 ldr r7, [r1, #vp8_blockd_dqcoeff] ; dqcoeff
32 ldr r8, [r1, #vp8_blockd_dequant] ; dequant
34 ldr r2, loop_count ; loop_count=0x1000000. 'lsls' instruction
43 ldr r9, [r3], #4 ; [z1 | z0]
44 ldr r10, [r5], #4 ; [r1 | r0]
45 ldr r11, [r4], #4 ; [q1 | q0
[all...] |
| /external/libvpx/libvpx/vp8/encoder/arm/armv5te/ |
| vp8_packtokens_armv5.asm | 30 ldr r2, [r0, #vp8_writer_buffer_end]
31 ldr r3, [r0, #vp8_writer_error]
54 ldr r2, [r0, #vp8_writer_lowvalue]
55 ldr r5, [r0, #vp8_writer_range]
56 ldr r3, [r0, #vp8_writer_count]
61 ldr r4, [sp, #8] ; vp8_coef_encodings
64 ldr r9, [r1, #tokenextra_context_tree] ; pp
68 ldr r6, [r4, #vp8_token_value] ; v
69 ldr r8, [r4, #vp8_token_len] ; n
77 ldr r10, [sp, #60] ; vp8_coef_tre
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| machine-licm.ll | 16 ; ARM: ldr [[REGISTER_1:r[0-9]+]], LCPI0_0
17 ; Unfortunately currently ARM codegen doesn't cse the ldr from constantpool.
18 ; The issue is it can be read by an "add pc" or a "ldr [pc]" so it's messy
20 ; time as the "ldr cp".
21 ; ARM: ldr r{{[0-9]+}}, LCPI0_1
23 ; ARM: ldr r{{[0-9]+}}, [pc, [[REGISTER_1]]]
24 ; ARM: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
30 ; MOVT: ldr r{{[0-9]+}}, [pc, [[REGISTER_2]]]
31 ; MOVT: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
43 ; THUMB: ldr.n r2, LCPI0_
[all...] |
| /external/llvm/test/MC/ARM/ |
| arm-shift-encoding.s | 3 ldr r0, [r0, r0]
4 ldr r0, [r0, r0, lsr #32]
5 ldr r0, [r0, r0, lsr #16]
6 ldr r0, [r0, r0, lsl #0]
7 ldr r0, [r0, r0, lsl #16]
8 ldr r0, [r0, r0, asr #32]
9 ldr r0, [r0, r0, asr #16]
10 ldr r0, [r0, r0, rrx]
11 ldr r0, [r0, r0, ror #16]
13 @ CHECK: ldr r0, [r0, r0] @ encoding: [0x00,0x00,0x90,0xe7
[all...] |
| /external/openssl/crypto/sha/asm/ |
| sha1-armv4-large.S | 14 ldr r8,.LK_00_19
33 ldr r9,[r1],#4 @ handles unaligned
58 ldr r9,[r1],#4 @ handles unaligned
83 ldr r9,[r1],#4 @ handles unaligned
108 ldr r9,[r1],#4 @ handles unaligned
133 ldr r9,[r1],#4 @ handles unaligned
161 ldr r9,[r1],#4 @ handles unaligned
174 ldr r9,[r14,#15*4]
175 ldr r10,[r14,#13*4]
176 ldr r11,[r14,#7*4
[all...] |
| /bionic/libc/arch-arm/syscalls/ |
| __brk.S | 8 ldr r7, =__NR_brk
|
| __fcntl.S | 8 ldr r7, =__NR_fcntl
|
| __fcntl64.S | 8 ldr r7, =__NR_fcntl64
|
| __fork.S | 8 ldr r7, =__NR_fork
|
| __fstatfs64.S | 8 ldr r7, =__NR_fstatfs64
|
| __getcpu.S | 8 ldr r7, =__NR_getcpu
|
| __getcwd.S | 8 ldr r7, =__NR_getcwd
|
