| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| omxVCM4P10_PredictIntraChroma_8x8_s.S | 29 LDR r6,[sp,#0x68]
30 LDR r4,[sp,#0x60]
31 LDR r5,[sp,#0x64]
32 LDR r7,[sp,#0x6c]
33 LDR r8,[r8,r6,LSL #2]
|
| /external/llvm/lib/Target/ARM/ |
| ARMJITInfo.cpp | 94 "ldr r0, [sp,#20]\n"
95 "ldr r1, [sp,#16]\n"
103 "ldr pc, [sp], #4\n"
123 // ldr pc, [pc,#-4]
128 *(intptr_t *)StubAddr = 0xe51ff004; // ldr pc, [pc, #-4]
184 JCE.emitWordLE(0xe59fc004); // ldr ip, [pc, #+4]
186 JCE.emitWordLE(0xe59cf000); // ldr pc, [ip]
199 JCE.emitWordLE(0xe51ff004); // ldr pc, [pc, #-4]
226 JCE.emitWordLE(0xe51ff004); // ldr pc, [pc, #-4]
|
| /external/openssl/crypto/sha/asm/ |
| sha1-armv4-large.pl | 77 ldr $t0,[$Xi,#15*4]
78 ldr $t1,[$Xi,#13*4]
79 ldr $t2,[$Xi,#7*4]
81 ldr $t3,[$Xi,#2*4]
110 ldr $t0,[$inp],#4 @ handles unaligned
166 ldr $K,.LK_00_19
189 ldr $K,.LK_20_39 @ [+15+16*4]
201 ldr $K,.LK_40_59
212 ldr $K,.LK_60_79
|
| /external/v8/src/arm/ |
| debug-arm.cc | 52 // ldr ip, [pc, #0]
56 // ldr pc, [pc, #-4]
62 patcher.masm()->ldr(v8::internal::ip, MemOperand(v8::internal::pc, 0));
66 patcher.masm()->ldr(v8::internal::pc, MemOperand(v8::internal::pc, -4));
103 // ldr ip, [pc, #0]
107 // ldr pc, [pc, #-4]
112 patcher.masm()->ldr(v8::internal::ip, MemOperand(v8::internal::pc, 0));
116 patcher.masm()->ldr(v8::internal::pc, MemOperand(v8::internal::pc, -4));
193 __ ldr(ip, MemOperand(ip));
|
| lithium-gap-resolver-arm.cc | 172 __ ldr(kSavedValueRegister, cgen_->ToMemOperand(source));
226 __ ldr(cgen_->ToRegister(destination), source_operand);
238 __ ldr(ip, source_operand);
242 __ ldr(kSavedValueRegister, source_operand);
292 __ ldr(kSavedValueRegister, source_operand);
294 __ ldr(kSavedValueRegister, source_high_operand);
|
| /bionic/libc/arch-arm/cortex-a9/bionic/ |
| strcmp.S | 96 use LDR and a shift queue. Order of loads and comparisons matters,
205 ldr r2, [r0], #4
250 ldr r2, [r0], #4
251 ldr r4, [r1], #4
264 ldr r5, [r1], #4
288 ldr r5, [r1], #4
293 ldr r3, [r0], #4
301 ldr r5, [r1], #4
386 ldr w1, [wp1], #4
387 ldr w2, [wp2], #
[all...] |
| /external/valgrind/main/exp-bbv/tests/arm-linux/ |
| ll.S | 34 ldr r11,data_addr
35 ldr r12,bss_addr
45 ldr r1,out_addr @ buffer we are printing to
51 ldr r8,logo_end_addr
53 ldr r9,text_addr @ r9 points to text buf
86 ldr r0,pos_mask @ urgh, can't handle simple constants
118 ldr r1,out_addr @ buffer we are printing to
131 ldr r10,out_addr @ point r10 to out_buffer
165 ldr r10,out_addr @ point r10 to out_buffer
203 ldr r3,[r11,#((sysinfo_buff-data_begin)+S_TOTALRAM)
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| fast-isel.ll | 149 ; THUMB: ldr r0, [r0]
150 ; THUMB: ldr r1, [r0]
156 ; ARM: ldr r0, [r0]
157 ; ARM: ldr r1, [r0]
214 ; ARM: ldr r0, [r0, #2]
217 ; THUMB: ldr.w r0, [r0, #2]
|
| arm-modifier.ll | 37 ; CHECK: ldr r0, [r{{[0-9]+}}]
38 call void asm sideeffect "ldr r0, [${0:m}]\0A\09", "*m,~{r0}"(i32** @f2_ptr) nounwind
|
| struct_byval.ll | 10 ; CHECK: ldr
22 ; CHECK: ldr
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| arm-tests.txt | 54 # CHECK: ldr r0, [r2], #15
57 # CHECK: ldr r5, [r7, -r10, lsl #2]
191 # CHECK: ldr r3, [pc, #144]
194 # CHECK: ldr r3, [r0, #-4]
197 # CHECK: ldr r5, [sp, r0, lsl #1]!
200 # CHECK: ldr r5, [r7], -r0, lsr #2
|
| /external/regex-re2/util/ |
| valgrind.h | [all...] |
| /external/v8/src/third_party/valgrind/ |
| valgrind.h | [all...] |
| /external/valgrind/main/include/ |
| valgrind.h | [all...] |
| /bionic/libc/arch-arm/bionic/ |
| memcpy.a15.S | 116 ldr r3, [r1], #4
162 ldr r3, [r1], #4
214 ldr r5, [r1], #4 /* Load a word from source. */
287 ldr r5, [r1]
348 /* Copy word by word using LDR when alignment can be done in hardware,
349 i.e., SCTLR.A is set, supporting unaligned access in LDR and STR. */
356 ldr r3, [r1, \offset]
374 ldr r3, [r1], #4
|
| /bionic/libc/arch-arm/cortex-a15/bionic/ |
| strcmp.S | 96 use LDR and a shift queue. Order of loads and comparisons matters,
205 ldr r2, [r0], #4
250 ldr r2, [r0], #4
251 ldr r4, [r1], #4
264 ldr r5, [r1], #4
288 ldr r5, [r1], #4
293 ldr r3, [r0], #4
301 ldr r5, [r1], #4
|
| /dalvik/vm/mterp/armv5te/ |
| OP_EXECUTE_INLINE_RANGE.S | 54 ldr r9, .L${opcode}_table @ table of InlineOperation
56 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry
|
| /external/llvm/lib/CodeGen/ |
| README.txt | 7 ldr lr, [r1, #+32]
9 ldr r4, [sp, #+52]
17 ldr lr, [r1, #+32]
25 ldr lr, [r1, #+32]
52 ldr r3, [sp, #+4]
54 ldr r2, [sp, #+8]
56 ldr r1, [sp, #+4] <==
58 ldr r0, [sp, #+4]
|
| /external/llvm/test/CodeGen/AArch64/ |
| tail-call.ll | 87 ; CHECK: ldr x0,
88 ; CHECK: ldr x1,
|
| /external/llvm/test/CodeGen/Mips/ |
| mips64load-store-left-right.ll | 15 ; EL: ldr $[[R0]], 0($[[R1]])
17 ; EB: ldr $[[R0]], 7($[[R1]])
|
| /external/llvm/test/CodeGen/Thumb/ |
| dyn-stackalloc.ll | 49 ; CHECK-NOT: ldr r0, [sp
53 ; CHECK-NOT: ldr r0, [sp
|
| /external/tremolo/Tremolo/ |
| floor1ARM.s | 53 LDR r4,[r1] @ r4 = *d
54 LDR r5,[r2],r3,LSL #2 @ r5 = *floor r2 = floor+base
|
| floor1LARM.s | 53 LDR r4, [r1] @ r4 = *d
54 LDR r5, [r2], r3,LSL #2 @ r5 = *floor r2 = floor+base
|
| /external/webkit/Source/WebCore/platform/graphics/filters/arm/ |
| FELightingNEON.cpp | 221 "ldr r0, [" PAINTING_DATA_R ", #" FLOAT_ARGUMENTS_OFFSET "]" NL
222 "ldr r1, [" PAINTING_DATA_R ", #" DRAWING_CONSTANTS_OFFSET "]" NL
223 "ldr " PIXELS_R ", [" PAINTING_DATA_R ", #" PIXELS_OFFSET "]" NL
224 "ldr " WIDTH_R ", [" PAINTING_DATA_R ", #" WIDTH_OFFSET "]" NL
225 "ldr " HEIGHT_R ", [" PAINTING_DATA_R ", #" HEIGHT_OFFSET "]" NL
226 "ldr " FLAGS_R ", [" PAINTING_DATA_R ", #" FLAGS_OFFSET "]" NL
227 "ldr " SPECULAR_EXPONENT_R ", [" PAINTING_DATA_R ", #" SPECULAR_EXPONENT_OFFSET "]" NL
228 "ldr " CONE_EXPONENT_R ", [" PAINTING_DATA_R ", #" CONE_EXPONENT_OFFSET "]" NL
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| Deemph_32_opt.s | 40 LDR r5, =22282 @r5---mu
46 LDR r5, [r3]
|
