| /external/valgrind/main/callgrind/tests/ |
| filter_stderr | 19 # Remove numbers from I1/D1/LL/LLi/LLd "misses:" and "miss rates:" lines
20 perl -p -e 's/((I1|D1|LL|LLi|LLd) *(misses|miss rate):)[ 0-9,()+rdw%\.]*$/\1/' |
|
| /frameworks/base/core/tests/coretests/src/android/widget/listview/ |
| ListHeterogeneousTest.java | 64 assertEquals("Unexpected convert misses", 0, convertMissesBefore);
72 assertEquals("Unexpected convert misses", 0, convertMissesAfter);
|
| /external/oprofile/events/mips/r12000/ |
| events | 13 event:0x9 counters:0,1,2,3 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
14 event:0xa counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_SECONDARY_CACHE_MISSES : Secondary cache misses (instruction)
21 event:0x11 counters:0,1,2,3 um:zero minimum:500 name:PREFETCH_MISSES_IN_DCACHE : Primary data cache misses by prefetch instructions
27 event:0x17 counters:0,1,2,3 um:zero minimum:500 name:TLB_MISSES : TLB misses
29 event:0x19 counters:0,1,2,3 um:zero minimum:500 name:DCACHE_MISSES : Primary data cache misses
30 event:0x1a counters:0,1,2,3 um:zero minimum:500 name:SCACHE_MISSES : Secondary cache misses (data)
|
| /external/oprofile/events/mips/24K/ |
| events.h | 7 "11-0 Data cache misses"},
83 "48-0 Refetches due to cache misses while both fill buffers already allocated"},
105 "5-1 Instruction micro-TLB misses"},
107 "6-1 Data micro-TLB misses"},
109 "7-1 Joint TLB instruction misses"},
111 "8-1 Joint TLB data (non-instruction) misses"},
113 "9-1 Instruction cache misses"},
|
| /external/oprofile/events/arm/armv6/ |
| events | 3 event:0x00 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
6 event:0x03 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of Instruction MicroTLB misses
7 event:0x04 counters:0,1 um:zero minimum:500 name:DTLB_MISS : number of Data MicroTLB misses
|
| /external/oprofile/events/arm/mpcore/ |
| events | 3 event:0x00 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
6 event:0x03 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
7 event:0x04 counters:0,1 um:zero minimum:500 name:DTLB_MISS : number of DTLB misses
|
| /external/oprofile/events/arm/xscale1/ |
| events | 3 event:0x00 counters:1,2 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
6 event:0x03 counters:1,2 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
7 event:0x04 counters:1,2 um:zero minimum:500 name:DTLB_MISS : number of DTLB misses
|
| /external/oprofile/events/arm/xscale2/ |
| events | 3 event:0x00 counters:1,2,3,4 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
6 event:0x03 counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
7 event:0x04 counters:1,2,3,4 um:zero minimum:500 name:DTLB_MISS : number of DTLB misses
|
| /external/oprofile/events/avr32/ |
| events | 3 event:0x00 counters:1,2 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
6 event:0x03 counters:1,2 um:zero minimum:500 name:ITLB_MISS : number of Instruction TLB misses
7 event:0x04 counters:1,2 um:zero minimum:500 name:DTLB_MISS : number of Data TLB misses
|
| /external/oprofile/events/i386/atom/ |
| unit_masks | 15 0x05 dtlb_miss_ld DTLB misses due to load operations
16 0x09 l0_dtlb_miss_ld L0_DTLB misses due to load operations
17 0x06 dtlb_miss_st DTLB misses due to store operations
44 0x02 misses Icache miss
47 0x02 misses ITLB misses
|
| /external/oprofile/events/ppc64/ibm-compat-v1/ |
| events | 42 event:0X0042 counters:2 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP4 : (Group 4 pm_compat_l1_dcache_load_store_miss) L1 D cache store misses
43 event:0X0043 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP4 : (Group 4 pm_compat_l1_dcache_load_store_miss) L1 D cache load misses
49 event:0X0053 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP5 : (Group 5 pm_compat_l1_cache_load) L1 D cache load misses
55 event:0X0063 counters:3 um:zero minimum:1000 name:PM_ITLB_MISS_GRP6 : (Group 6 pm_compat_instruction_directory) Instruction TLB misses
59 event:0X0071 counters:1 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP7 : (Group 7 pm_compat_data_directory) DERAT misses
60 event:0X0072 counters:2 um:zero minimum:1000 name:PM_DTLB_MISS_GRP7 : (Group 7 pm_compat_data_directory) Data TLB misses
|
| /external/oprofile/events/alpha/ev4/ |
| events | 11 event:0x10 counters:0 um:zero minimum:256 name:DCACHE_MISSES : Total D-cache misses
12 event:0x11 counters:0 um:zero minimum:256 name:ICACHE_MISSES : Total I-cache misses
|
| /external/oprofile/events/i386/westmere/ |
| unit_masks | 64 0x01 any DTLB load misses
71 0x01 any DTLB misses
74 0x10 stlb_hit DTLB first level misses but second level hit
75 0x20 pde_miss DTLB misses casued by low part of address
116 0x02 miss L1D hardware prefetch misses
119 0x01 i_state L1 writebacks to L2 in I state (misses)
126 0x02 misses L1I instruction fetch misses
130 0x01 demand_i_state L2 data demand loads in I state (misses)
135 0x10 prefetch_i_state L2 data prefetches in the I state (misses)
[all...] |
| /external/icu4c/i18n/ |
| csr2022.cpp | 38 int32_t misses = 0; local
69 misses += 1;
90 quality = (100*hits - 100*misses) / (hits + misses);
|
| /external/iproute2/doc/ |
| rtstat.sgml | 18 in a vmstat or iostat manner. The ratio between cache hits and misses gives
|
| /external/webkit/LayoutTests/http/tests/appcache/ |
| top-frame-1.html | 6 anyway, so it can also pass if the UA fails to reject loads for cache misses.</p>
|
| /external/oprofile/events/mips/1004K/ |
| events.h | 7 "11-0 Data cache misses"},
93 "48-0 Refetches due to cache misses while both fill buffers already allocated"},
129 "5-1 Instruction micro-TLB misses"},
131 "6-1 Data micro-TLB misses"},
133 "7-1 Joint TLB instruction misses"},
135 "8-1 Joint TLB data (non-instruction) misses"},
137 "9-1 Instruction cache misses"},
|
| /external/oprofile/events/mips/34K/ |
| events.h | 7 "11-0 Data cache misses"},
91 "48-0 Refetches due to cache misses while both fill buffers already allocated"},
115 "5-1 Instruction micro-TLB misses"},
117 "6-1 Data micro-TLB misses"},
119 "7-1 Joint TLB instruction misses"},
121 "8-1 Joint TLB data (non-instruction) misses"},
123 "9-1 Instruction cache misses"},
|
| /external/guava/guava/src/com/google/common/cache/ |
| CacheStats.java | 115 * value can result in multiple misses, all returning the results of a single cache load
123 * Returns the ratio of cache requests which were misses. This is defined as
125 * Note that {@code hitRate + missRate =~ 1.0}. Cache misses include all requests which
129 * concurrent misses for the same key will result in a single load operation.
149 * {@link #loadExceptionCount}). Multiple concurrent misses for the same key will result in a
160 * {@link #loadSuccessCount}). Multiple concurrent misses for the same key will result in a
|
| /external/oprofile/events/ppc64/power5++/ |
| events | 152 event:0X0160 counters:0 um:zero minimum:1000 name:PM_ITLB_MISS_GRP22 : (Group 22 pm_flush2) Instruction TLB misses
265 #Group 41 pm_ic_miss, ICache misses
271 #Group 42 pm_branch_miss, Branch mispredict, TLB and SLB misses
272 event:0X02A0 counters:0 um:zero minimum:1000 name:PM_TLB_MISS_GRP42 : (Group 42 pm_branch_miss) TLB misses
273 event:0X02A1 counters:1 um:zero minimum:1000 name:PM_SLB_MISS_GRP42 : (Group 42 pm_branch_miss) SLB misses
289 #Group 45 pm_L1_tlbmiss, L1 load and TLB misses
291 event:0X02D1 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_GRP45 : (Group 45 pm_L1_tlbmiss) Data TLB misses
292 event:0X02D2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP45 : (Group 45 pm_L1_tlbmiss) L1 D cache load misses
295 #Group 46 pm_L1_DERAT_miss, L1 store and DERAT misses
297 event:0X02E1 counters:1 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP46 : (Group 46 pm_L1_DERAT_miss) DERAT misses
[all...] |
| /external/oprofile/events/arm/armv7-common/ |
| events | 5 event:0x01 counters:1,2,3,4,5,6 um:zero minimum:500 name:IFETCH_MISS : Instruction fetch misses from cache or normal cacheable memory
6 event:0x02 counters:1,2,3,4,5,6 um:zero minimum:500 name:ITLB_MISS : Instruction fetch misses from TLB
|
| /external/oprofile/events/mips/74K/ |
| events.h | 57 "29-0 L2 Cache Misses"},
139 "4-1 Instruction micro-TLB misses"},
141 "5-1 Joint TLB instruction misses"},
143 "6-1 Instruction cache misses, includes misses from fetch-ahead and speculation"},
173 "24-1 Data cache misses"},
175 "25-1 Joint TLB data (non-instruction) misses"},
179 "27-1 Load/store graduations not resulting in a bus request because misses at integer pipe graduation turn into hit or merge with outstanding fill request"},
|
| /external/oprofile/events/ppc64/970MP/ |
| events | 35 event:0X0022 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP2 : (Group 2 pm_eprof) L1 D cache load misses
45 event:0X0032 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP3 : (Group 3 pm_basic) L1 D cache load misses
179 event:0X0106 counters:6 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP16 : (Group 16 pm_lsu_load1) LSU0 L1 D cache load misses
180 event:0X0107 counters:7 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP16 : (Group 16 pm_lsu_load1) LSU1 L1 D cache load misses
189 event:0X0116 counters:6 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP17 : (Group 17 pm_lsu_store1) L1 D cache store misses
203 event:0X0130 counters:0 um:zero minimum:1000 name:PM_LSU0_DERAT_MISS_GRP19 : (Group 19 pm_lsu7) LSU0 DERAT misses
204 event:0X0131 counters:1 um:zero minimum:1000 name:PM_LSU1_DERAT_MISS_GRP19 : (Group 19 pm_lsu7) LSU1 DERAT misses
233 event:0X0160 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP22 : (Group 22 pm_pe_bench4) Data TLB misses
234 event:0X0161 counters:1 um:zero minimum:1000 name:PM_ITLB_MISS_GRP22 : (Group 22 pm_pe_bench4) Instruction TLB misses
235 event:0X0162 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache load misses
[all...] |
| /external/oprofile/events/i386/nehalem/ |
| unit_masks | 24 0x01 any Counts all load misses that cause a page walk
27 0x20 pde_miss Number of DTLB cache load misses where the low part of the linear to physical address translation was missed
28 0x40 pdp_miss Number of DTLB cache load misses where the high part of the linear to physical address translation was missed
91 0x80 prefetch_miss Counts L2 prefetch misses for both code and data
93 0xAA miss Counts all L2 misses for both code and data
155 0x01 any Counts the number of misses in the STLB which causes a page walk
156 0x02 walk_completed Counts number of misses in the STLB which resulted in a completed page walk
157 0x10 stlb_hit Counts the number of DTLB first level misses that hit in the second level TLB
158 0x20 pde_miss Number of DTLB cache misses where the low part of the linear to physical address translation was missed
159 0x40 pdp_miss Number of DTLB misses where the high part of the linear to physical address translation was misse
[all...] |
| /external/bzip2/ |
| mk251.c | 4 1007 in blocksort.c. This assertion misses an extremely rare
|
