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  /prebuilts/ndk/5/platforms/android-3/arch-arm/usr/lib/
libdl.so 
libthread_db.so 
  /prebuilts/ndk/5/platforms/android-8/arch-arm/usr/lib/
libdl.so 
  /prebuilts/ndk/6/platforms/android-3/arch-arm/usr/lib/
libdl.so 
libthread_db.so 
  /prebuilts/ndk/6/platforms/android-8/arch-arm/usr/lib/
libdl.so 
  /external/llvm/include/llvm/CodeGen/
RegisterClassInfo.h 46 OwningArrayPtr<RCInfo> RegClass;
70 const RCInfo &RCI = RegClass[RC->getID()];
  /external/llvm/lib/Target/ARM/
Thumb1InstrInfo.cpp 58 isARMLowRegister(SrcReg))) && "Unknown regclass!");
86 isARMLowRegister(DestReg))) && "Unknown regclass!");
  /external/llvm/lib/Target/AArch64/
AArch64AsmPrinter.cpp 45 const TargetRegisterClass &RegClass,
51 if (RegClass.contains(*AR)) {
63 const TargetRegisterClass &RegClass,
65 char Prefix = &RegClass == &AArch64::GPR32RegClass ? 'w' : 'x';
77 if (RegClass.contains(*AR)) {
AArch64FrameLowering.h 31 const TargetRegisterClass *RegClass; // E.g. GPR64RegClass
AArch64InstrInfo.cpp 402 llvm_unreachable("Unknown size for regclass");
413 llvm_unreachable("Unknown size for regclass");
448 llvm_unreachable("Unknown size for regclass");
459 llvm_unreachable("Unknown size for regclass");
  /development/ndk/tests/prebuilt-library/jni/
libfoo.so 
  /external/llvm/test/CodeGen/X86/
h-registers-0.ll 13 ; See FIXME: on regclass GR8.
  /prebuilts/ndk/4/platforms/android-3/arch-arm/usr/lib/
libthread_db.so 
  /prebuilts/ndk/4/platforms/android-4/arch-arm/usr/lib/
libthread_db.so 
  /prebuilts/ndk/4/platforms/android-5/arch-arm/usr/lib/
libthread_db.so 
  /prebuilts/ndk/4/platforms/android-8/arch-arm/usr/lib/
libthread_db.so 
  /external/llvm/lib/Target/R600/
SIInstrInfo.td 265 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
268 (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
278 class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
280 (outs regClass:$dst),
291 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
293 (outs regClass:$dst),
R600MachineScheduler.cpp 330 // and we try to constraint its regclass
338 // Constrains the regclass of DestReg to assign it to Slot
AMDGPUInstrInfo.cpp 255 // Convert dst regclass to one that is supported by the ISA
  /dalvik/vm/compiler/codegen/mips/
Ralloc.h 84 int regClass, bool update);
  /external/llvm/include/llvm/Target/
TargetOpcodes.h 76 // pair. Once it has been lowered to a MachineInstr, the regclass operand
  /external/llvm/utils/TableGen/
RegisterInfoEmitter.cpp     [all...]
  /external/llvm/lib/CodeGen/
TargetInstrInfo.cpp 45 short RegClass = MCID.OpInfo[OpNum].RegClass;
47 return TRI->getPointerRegClass(MF, RegClass);
50 if (RegClass < 0)
54 return TRI->getRegClass(RegClass);
AggressiveAntiDepBreaker.h 160 /// Keep track of a position in the allocation order for each regclass.

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