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  /external/llvm/lib/CodeGen/
AggressiveAntiDepBreaker.h 42 /// Operand - The registers operand
49 /// NumTargetRegs - Number of non-virtual target registers
63 /// composed of registers that are not eligible for anti-aliasing.
66 /// RegRefs - Map registers to all their references within a live range.
93 // GetGroupRegs - Return a vector of the registers belonging to a
94 // group. If RegRefs is non-NULL then only included referenced registers.
108 // representing the registers new group.
124 /// CriticalPathSet - The set of registers that should only be
129 /// registers.
143 /// of the ScheduleDAG and break them by renaming registers
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  /external/webkit/Source/JavaScriptCore/dfg/
DFGGenerationInfo.h 55 // Can provide information as to whether a value is in machine registers, and if so which,
59 // so that we know when the value is dead and the machine registers associated with it
132 // associated machine registers may be freed.
147 // Get the format of the value in machine registers (or 'none').
156 // Check whether a value needs spilling in order to free up any associated machine registers.
172 // We should only be spilling values that are currently in machine registers.
184 // already been spilled), to mark them as no longer being in machine registers.
187 // Should only be called on values that don't need spilling, and are currently in registers.
192 // Record that this value is filled into machine registers,
193 // tracking which registers, and what format the value has
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  /external/llvm/include/llvm/Target/
TargetRegisterInfo.h 59 /// begin/end - Return all of the registers in this class.
64 /// getNumRegs - Return the number of registers in this class.
75 /// register class. This does not include virtual registers.
80 /// contains - Return true if both registers are in this class.
93 /// getCopyCost - Return the cost of copying a value between two registers in
99 /// virtual registers.
181 /// registers from this register class in MF. The raw order comes directly
182 /// from the .td file and may include reserved registers that are not
184 /// callee-saved registers only after all the volatiles are used. The
186 /// callee-saved registers moved to the end
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  /external/llvm/lib/Target/X86/
X86CallingConv.td 34 // integer values in registers.
42 // registers, it won't have vector types.
98 // No more than 4 registers
190 // The first 6 integer arguments are passed in integer registers.
194 // The first 8 MMX vector arguments are passed in XMM registers on Darwin.
200 // The first 8 FP/Vector arguments are passed in XMM registers.
205 // The first 8 256-bit vector arguments are passed in YMM registers, unless
209 // registers. Actually modeling that would be a lot of work, though.
216 // 8-byte aligned if there are no more registers to hold them.
252 // The first 4 integer arguments are passed in integer registers
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  /external/smali/smali-integration-tests/src/test/smali/junit-tests/AnnotationTests/
AnnotationTests.smali 6 .registers 1
29 .registers 2
53 .registers 4
81 .registers 5
116 .registers 4
152 .registers 2
164 .registers 6
  /external/v8/src/arm/
constants-arm.cc 61 const char* Registers::names_[kNumRegisters] = {
67 // List of alias names which can be used when referring to ARM registers.
68 const Registers::RegisterAlias Registers::aliases_[] = {
79 const char* Registers::Name(int reg) {
90 // Support for VFP registers s0 to s31 (d0 to d15).
128 int Registers::Number(const char* name) {
frames-arm.h 46 // Caller-saved/arguments registers
62 // Callee-saved registers preserved when switching from C to JavaScript
85 // Double registers d8 to d15 are callee-saved.
89 // Number of registers for which space is reserved in safepoints. Must be a
91 // TODO(regis): Only 8 registers may actually be sufficient. Revisit.
94 // Define the list of registers actually saved at safepoints.
95 // Note that the number of saved registers may be smaller than the reserved
  /external/webkit/Source/JavaScriptCore/runtime/
JSVariableObject.h 69 JSVariableObject(JSGlobalData& globalData, Structure* structure, SymbolTable* symbolTable, Register* registers)
72 , m_registers(reinterpret_cast<WriteBarrier<Unknown>*>(registers))
79 void setRegisters(WriteBarrier<Unknown>* registers, PassOwnArrayPtr<WriteBarrier<Unknown> > registerArray);
89 OwnArrayPtr<WriteBarrier<Unknown> > m_registerArray; // Independent copy of registers, used when a variable object copies its registers out of the register file.
151 inline void JSVariableObject::setRegisters(WriteBarrier<Unknown>* registers, PassOwnArrayPtr<WriteBarrier<Unknown> > registerArray)
155 m_registers = registers;
  /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/asm/
user_64.h 9 contents of the floating point registers, and until these are
12 the user struct to find out what the floating point registers
19 All of the registers are stored as part of the upage. The upage should
80 /* We start with the registers, to mimic the way that "memory" is returned
82 struct user_regs_struct regs; /* Where the registers are actually stored */
87 struct user_i387_struct i387; /* Math Co-processor registers. */
101 /* the registers. */
  /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/asm/
user_64.h 9 contents of the floating point registers, and until these are
12 the user struct to find out what the floating point registers
19 All of the registers are stored as part of the upage. The upage should
80 /* We start with the registers, to mimic the way that "memory" is returned
82 struct user_regs_struct regs; /* Where the registers are actually stored */
87 struct user_i387_struct i387; /* Math Co-processor registers. */
101 /* the registers. */
  /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/asm/
user_64.h 9 contents of the floating point registers, and until these are
12 the user struct to find out what the floating point registers
19 All of the registers are stored as part of the upage. The upage should
80 /* We start with the registers, to mimic the way that "memory" is returned
82 struct user_regs_struct regs; /* Where the registers are actually stored */
87 struct user_i387_struct i387; /* Math Co-processor registers. */
101 /* the registers. */
  /external/smali/smali-integration-tests/src/test/smali/jumbo-field-tests/
Format52c.smali 35 .registers 1
41 .registers 259
60 .registers 259
82 .registers 261
102 .registers 259
122 .registers 259
142 .registers 259
162 .registers 259
182 .registers 259
  /external/chromium/chrome/browser/custom_handlers/
protocol_handler_registry.h 60 // Registers the preferences that we store registered protocol handlers in.
77 // Registers a new protocol handler.
80 // Registers a new protocol handler from a JSON dictionary.
  /external/clang/test/CodeGen/
mips-constraint-regs.c 11 // registers. We are looking for syntactical correctness.
32 // 'x': Combined lo/hi registers
33 // We are specifying that destination registers are the hi/lo pair with the
  /external/kernel-headers/original/asm-arm/
ucontext.h 7 * struct sigcontext only has room for the basic registers, but struct
8 * ucontext now has room for all registers which need to be saved and
9 * restored. Coprocessor registers are stored in uc_regspace. Each
  /external/llvm/test/MC/Mips/
nabi-regs.s 2 # set for the A and T registers because the NABI allows
3 # for 4 more register parameters (A registers) offsetting
4 # the T registers.
  /external/smali/smali-integration-tests/src/test/smali/jumbo-method-tests/
zzzRangeMethodsSuper_autofix.smali 34 .registers 1
40 .registers 7
52 .registers 7
  /external/valgrind/main/memcheck/tests/
leak.h 45 * into registers. Valgrind may consider these registers when determining
46 * whether an address is reachable, so we need to zero-out these registers
  /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/
omxVCM4P10_DequantTransformResidualFromPairAndAdd_s.s 37 ;//Input Registers
42 ;//Output Registers
45 ;//Local Scratch Registers
103 ;// All the 16 src values are loaded at once into 8 registers : SrcDst<y><x> (above)
182 ;//Input Registers
187 ;//Output Registers
190 ;//Local Scratch Registers
246 ;// All the 16 src values are loaded at once into 8 registers : SrcDst<y><x> (above)
330 ;//Input Registers
337 ;//Output Registers
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  /system/core/libcorkscrew/arch-x86/
dwarf.h 117 /* Dwarf preserved number of registers for x86. */
125 reg_rule_t regs[DWARF_REGISTERS]; // dwarf preserved registers for x86
128 /* DWARF registers we are caring about. */
  /system/extras/tests/bionic/libc/bionic/
test_setjmp.c 44 /* test that integer registers are restored properly */
56 fprintf(stderr, "setjmp() is broken for integer registers !\n");
74 fprintf(stderr, "setjmp() is broken for floating point registers !\n");
  /external/llvm/lib/Target/AArch64/
AArch64CallingConv.td 29 // registers are passed and returned via the natural LLVM type.
31 // registers as similar integer or composite types. For example:
33 // * HFAs in registers follow rules similar to small structs: appropriate
40 // struct doesn't later use integer registers.
43 // PCS compliance) to check whether enough registers are available for an
60 // registers. This makes sense because the PCS does not distinguish Short
79 // SIMD and Floating-point registers (NSRN - number of elements < 8), then the
80 // argument is allocated to SIMD and Floating-point registers (with one
82 // registers used. The argument has now been allocated."
114 // First we implement C.8 and C.9 (128-bit types get even registers). i128 i
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  /bionic/libc/arch-mips/include/machine/
regdef.h 44 #define a0 $4 /* argument registers */
57 #define t0 $12 /* temp registers (not saved across subroutine calls) */
62 #define t0 $8 /* temp registers (not saved across subroutine calls) */
83 #define t8 $24 /* two more temp registers */
  /dalvik/dx/src/com/android/dx/ssa/
SetFactory.java 48 * {@link SsaBasicBlock}. These are sets of SSA registers kept per basic
52 * times the size of registers. The threshold value here is merely
75 * @param countRegs {@code >=0;} count of SSA registers used in method
87 * @param countRegs {@code >=0;} count of SSA registers used in method
SsaRenamer.java 34 * Complete transformation to SSA form by renaming all registers accessed.<p>
39 * to a new flat (versionless) register space. The "version 0" registers,
40 * which represent the initial state of the Rop registers and should never
42 * as the first N registers in the SSA namespace. Subsequent assignments
45 * two adjoining Rop registers. This adjoining register representation is
51 * representation means that unaligned accesses to 64-bit registers are not
72 /** the number of original rop registers */
75 /** work only on registers above this value */
90 * maps SSA registers back to the original rop number. Used for
107 * Reserve the first N registers in the SSA register space fo
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