| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
243 if (Reg == 0 || Reg == X86::RIP) continue;
273 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
306 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| h-registers-0.ll | 1 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X86-64
3 ; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X86-32
5 ; Use h registers. On x86-64, codegen doesn't support general allocation
6 ; of h registers yet, due to x86 encoding complications.
9 ; X86-64: bar64:
10 ; X86-64: shrq $8, %rdi
11 ; X86-64: incb %dil
19 ; X86-32: bar64:
20 ; X86-32: incb %a
[all...] |
| fsgsbase.ll | 1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86-64 -mcpu=core-avx-i -mattr=fsgsbase | FileCheck %s
5 %res = call i32 @llvm.x86.rdfsbase.32()
8 declare i32 @llvm.x86.rdfsbase.32() nounwind readnone
12 %res = call i32 @llvm.x86.rdgsbase.32()
15 declare i32 @llvm.x86.rdgsbase.32() nounwind readnone
19 %res = call i64 @llvm.x86.rdfsbase.64()
22 declare i64 @llvm.x86.rdfsbase.64() nounwind readnone
26 %res = call i64 @llvm.x86.rdgsbase.64()
29 declare i64 @llvm.x86.rdgsbase.64() nounwind readnone
33 call void @llvm.x86.wrfsbase.32(i32 %x
[all...] |
| /external/libffi/linux-x86/ |
| ffi.h | 6 #define X86 1
9 #include "../src/x86/ffitarget.h"
|
| /external/valgrind/main/none/tests/x86/ |
| insn_cmov.vgtest | 1 prog: ../../../none/tests/x86/insn_cmov
2 prereq: ../../../tests/x86_amd64_features x86-cmov
|
| insn_fpu.vgtest | 1 prog: ../../../none/tests/x86/insn_fpu
2 prereq: ../../../tests/x86_amd64_features x86-fpu
|
| insn_mmx.vgtest | 1 prog: ../../../none/tests/x86/insn_mmx
2 prereq: ../../../tests/x86_amd64_features x86-mmx
|
| insn_mmxext.vgtest | 1 prog: ../../../none/tests/x86/insn_mmxext
2 prereq: ../../../tests/x86_amd64_features x86-mmxext
|
| insn_sse.vgtest | 1 prog: ../../../none/tests/x86/insn_sse
2 prereq: ../../../tests/x86_amd64_features x86-sse
|
| insn_sse2.vgtest | 1 prog: ../../../none/tests/x86/insn_sse2
2 prereq: ../../../tests/x86_amd64_features x86-sse2
|
| insn_sse3.vgtest | 1 prog: ../../../none/tests/x86/insn_sse3
2 prereq: ../../../tests/x86_amd64_features x86-sse3
|
| insn_ssse3.vgtest | 1 prog: ../../../none/tests/x86/insn_ssse3
2 prereq: test -x insn_ssse3 && ../../../tests/x86_amd64_features x86-ssse3
|
| /dalvik/vm/mterp/x86/ |
| OP_ADD_FLOAT.S | 2 %include "x86/binflop.S" {"instr":"fadds","load":"flds","store":"fstps"}
|
| OP_ADD_FLOAT_2ADDR.S | 2 %include "x86/binflop2addr.S" {"instr":"fadds","load":"flds","store":"fstps"}
|
| OP_ADD_INT.S | 2 %include "x86/binop.S" {"instr":"addl (rFP,%ecx,4),%eax"}
|
| OP_ADD_INT_2ADDR.S | 2 %include "x86/binop2addr.S" {"instr":"addl %eax,(rFP,%ecx,4)"}
|
| OP_AND_INT.S | 2 %include "x86/binop.S" {"instr":"andl (rFP,%ecx,4),%eax"}
|
| OP_AND_INT_2ADDR.S | 2 %include "x86/binop2addr.S" {"instr":"andl %eax,(rFP,%ecx,4)"}
|
| OP_APUT_BOOLEAN.S | 2 %include "x86/OP_APUT.S" {"reg":"rINSTbl", "store":"movb", "shift":"1" }
|
| OP_APUT_BYTE.S | 2 %include "x86/OP_APUT.S" { "reg":"rINSTbl", "store":"movb", "shift":"1" }
|
| OP_APUT_CHAR.S | 2 %include "x86/OP_APUT.S" { "reg":"rINSTw", "store":"movw", "shift":"2" }
|
| OP_APUT_SHORT.S | 2 %include "x86/OP_APUT.S" { "reg":"rINSTw", "store":"movw", "shift":"2" }
|
| OP_DIV_DOUBLE.S | 2 %include "x86/binflop.S" {"instr":"fdivl","load":"fldl","store":"fstpl"}
|
| OP_DIV_DOUBLE_2ADDR.S | 2 %include "x86/binflop2addr.S" {"instr":"fdivl","load":"fldl","store":"fstpl"}
|
| OP_DIV_FLOAT.S | 2 %include "x86/binflop.S" {"instr":"fdivs","load":"flds","store":"fstps"}
|
