| /external/llvm/test/CodeGen/X86/ |
| barrier-sse.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep sfence
2 ; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep lfence
3 ; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep mfence
4 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep MEMBARRIER
|
| lfence.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep lfence
3 declare void @llvm.x86.sse2.lfence() nounwind
6 call void @llvm.x86.sse2.lfence()
|
| mfence.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep sfence
2 ; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep lfence
3 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep mfence
|
| mmx-emms.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+mmx | grep emms
4 call void @llvm.x86.mmx.emms( )
11 declare void @llvm.x86.mmx.emms()
|
| sfence.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep sfence
3 declare void @llvm.x86.sse.sfence() nounwind
6 call void @llvm.x86.sse.sfence()
|
| int-intrinsic.ll | 1 ; RUN: llc < %s -march=x86 | FileCheck %s
2 ; RUN: llc < %s -march=x86-64 | FileCheck %s
4 declare void @llvm.x86.int(i8) nounwind
10 call void @llvm.x86.int(i8 3) nounwind
18 call void @llvm.x86.int(i8 128) nounwind
|
| byval.ll | 1 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck -check-prefix=X86-64 %s
3 ; RUN: llc < %s -march=x86 | FileCheck -check-prefix=X86 %s
5 ; X86: movl 4(%esp), %eax
6 ; X86: movl 8(%esp), %edx
8 ; X86-64: movq 8(%rsp), %rax
|
| rtm.ll | 3 declare i32 @llvm.x86.xbegin() nounwind
4 declare void @llvm.x86.xend() nounwind
5 declare void @llvm.x86.xabort(i8) noreturn nounwind
9 %0 = tail call i32 @llvm.x86.xbegin() nounwind
18 tail call void @llvm.x86.xend() nounwind
26 tail call void @llvm.x86.xabort(i8 2)
|
| /external/valgrind/main/none/tests/x86/ |
| cse_fail.vgtest | 2 prereq: ../../../tests/x86_amd64_features x86-sse
|
| lzcnt32.vgtest | 2 prereq: ../../../tests/x86_amd64_features x86-lzcnt
|
| /external/llvm/test/Bitcode/ |
| ptest-new.ll | 5 ; CHECK: call i32 @llvm.x86.sse41.ptestc(<2 x i64>
6 %res1 = call i32 @llvm.x86.sse41.ptestc(<2 x i64> %bar, <2 x i64> %bar)
7 ; CHECK: call i32 @llvm.x86.sse41.ptestz(<2 x i64>
8 %res2 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %bar, <2 x i64> %bar)
9 ; CHECK: call i32 @llvm.x86.sse41.ptestnzc(<2 x i64>
10 %res3 = call i32 @llvm.x86.sse41.ptestnzc(<2 x i64> %bar, <2 x i64> %bar)
16 ; CHECK: declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) #1
17 ; CHECK: declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) #1
18 ; CHECK: declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) #1
20 declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnon
[all...] |
| ptest-old.ll | 5 ; CHECK: call i32 @llvm.x86.sse41.ptestc(<2 x i64>
6 %res1 = call i32 @llvm.x86.sse41.ptestc(<4 x float> %bar, <4 x float> %bar)
7 ; CHECK: call i32 @llvm.x86.sse41.ptestz(<2 x i64>
8 %res2 = call i32 @llvm.x86.sse41.ptestz(<4 x float> %bar, <4 x float> %bar)
9 ; CHECK: call i32 @llvm.x86.sse41.ptestnzc(<2 x i64>
10 %res3 = call i32 @llvm.x86.sse41.ptestnzc(<4 x float> %bar, <4 x float> %bar)
16 ; CHECK: declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) #1
17 ; CHECK: declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) #1
18 ; CHECK: declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) #1
20 declare i32 @llvm.x86.sse41.ptestc(<4 x float>, <4 x float>) nounwind readnon
[all...] |
| /build/core/combo/arch/x86/ |
| x86-atom.mk | 2 # 'x86-atom' arch variant. This is an extension of the 'x86' base variant
5 # See build/core/combo/arch/x86/x86.mk for differences.
|
| /dalvik/vm/mterp/x86/ |
| OP_ADD_LONG.S | 2 %include "x86/binopWide.S" {"instr1":"addl (rFP,%ecx,4),rIBASE", "instr2":"adcl 4(rFP,%ecx,4),%eax"}
|
| OP_ADD_LONG_2ADDR.S | 2 %include "x86/binopWide2addr.S" {"instr1":"addl %eax,(rFP,rINST,4)","instr2":"adcl %ecx,4(rFP,rINST,4)"}
|
| OP_AND_LONG.S | 2 %include "x86/binopWide.S" {"instr1":"andl (rFP,%ecx,4),rIBASE", "instr2":"andl 4(rFP,%ecx,4),%eax"}
|
| OP_AND_LONG_2ADDR.S | 2 %include "x86/binopWide2addr.S" {"instr1":"andl %eax,(rFP,rINST,4)","instr2":"andl %ecx,4(rFP,rINST,4)"}
|
| OP_IGET_BYTE.S | 3 %include "x86/OP_IGET.S" { "load":"movsbl", "sqnum":"2" }
|
| OP_IGET_CHAR.S | 3 %include "x86/OP_IGET.S" { "load":"movzwl", "sqnum":"3" }
|
| OP_IGET_SHORT.S | 3 %include "x86/OP_IGET.S" { "load":"movswl", "sqnum":"4" }
|
| OP_LONG_TO_INT.S | 3 %include "x86/OP_MOVE.S"
|
| OP_OR_LONG.S | 2 %include "x86/binopWide.S" {"instr1":"orl (rFP,%ecx,4),rIBASE", "instr2":"orl 4(rFP,%ecx,4),%eax"}
|
| OP_OR_LONG_2ADDR.S | 2 %include "x86/binopWide2addr.S" {"instr1":"orl %eax,(rFP,rINST,4)","instr2":"orl %ecx,4(rFP,rINST,4)"}
|
| OP_SUB_LONG.S | 2 %include "x86/binopWide.S" {"instr1":"subl (rFP,%ecx,4),rIBASE", "instr2":"sbbl 4(rFP,%ecx,4),%eax"}
|
| OP_SUB_LONG_2ADDR.S | 2 %include "x86/binopWide2addr.S" {"instr1":"subl %eax,(rFP,rINST,4)","instr2":"sbbl %ecx,4(rFP,rINST,4)"}
|
