| /external/llvm/include/llvm/CodeGen/ |
| ScheduleDAG.h | 36 class SDNode;
272 SDNode *Node; // Representative node.
328 /// an SDNode and any nodes flagged to it.
329 SUnit(SDNode *node, unsigned nodenum)
377 /// setNode - Assign the representative SDNode for this SUnit.
379 void setNode(SDNode *N) {
380 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
384 /// getNode - Return the representative SDNode for this SUnit.
386 SDNode *getNode() const {
387 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!")
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 255 static SDNode *findUser(SDValue Value, unsigned Opcode) {
257 SDNode *Parent = Value.getNode();
258 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
277 SDNode *Intr = BRCOND.getOperand(1).getNode();
279 SDNode *BR = 0;
283 SDNode *SetCC = Intr;
310 SDNode *Result = DAG.getNode(
327 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
371 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
433 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const
[all...] |
| AMDILISelDAGToDAG.cpp | 45 SDNode *Select(SDNode *N);
158 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
237 for (SDNode::use_iterator Use = N->use_begin(), Next = llvm::next(Use);
238 Use != SDNode::use_end(); Use = Next) {
289 SDNode *Result = SelectCode(N);
306 for(SDNode::op_iterator I = Result->op_begin(), E = Result->op_end();
317 SDNode *PotentialClamp = *Result->use_begin();
638 SDNode *ResNode = Lowering.PostISelFolding(Node, *CurDAG)
[all...] |
| AMDGPUISelLowering.h | 65 virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const {
|
| R600InstrInfo.h | 117 SDNode *Node) const { return 1;}
|
| R600ISelLowering.cpp | 443 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
451 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
460 SDNode *Node = LowerSTORE(SDValue(N, 0), DAG).getNode();
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 169 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
173 inline bool immSext8(SDNode *N) const {
179 inline bool i64immSExt32(SDNode *N) const {
188 SDNode *Select(SDNode *N);
189 SDNode *SelectGather(SDNode *N, unsigned Opc);
190 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc)
[all...] |
| X86ISelLowering.h | 433 bool isVEXTRACTF128Index(SDNode *N);
438 bool isVINSERTF128Index(SDNode *N);
443 unsigned getExtractVEXTRACTF128Immediate(SDNode *N);
448 unsigned getInsertVINSERTF128Immediate(SDNode *N);
531 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
535 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
576 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.h | 145 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
|
| HexagonCallingConvLower.h | 31 class SDNode;
|
| HexagonISelLowering.cpp | 347 /// being lowered. Returns a SDNode with the same number of values as the
600 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
621 static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) {
638 bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
675 SDNode *Node = Op.getNode();
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 167 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 242 SUnit *CreateNewSUnit(SDNode *N) {
285 const SDNode *Node = RegDefPos.GetNode();
406 static bool IsChainDependent(SDNode *Outer, SDNode *Inner,
409 SDNode *N = Outer;
456 static SDNode *
457 FindCallSeqStart(SDNode *N, unsigned &NestLevel, unsigned &MaxNest,
464 SDNode *Best = 0;
469 if (SDNode *New = FindCallSeqStart(N->getOperand(i).getNode(),
550 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()
[all...] |
| ResourcePriorityQueue.cpp | 79 const SDNode *ScegN = PredSU->getNode();
117 const SDNode *ScegN = SuccSU->getNode();
448 for (SDNode *N = SU->getNode(); N; N = N->getGluedNode()) {
482 const SDNode *ScegN = SU->getNode();
551 for (SDNode *N = SU->getNode(); N; N = N->getGluedNode())
|
| LegalizeDAG.cpp | 59 SmallPtrSet<SDNode *, 16> LegalizedNodes;
70 void LegalizeOp(SDNode *Node);
74 void LegalizeLoadOps(SDNode *Node);
75 void LegalizeStoreOps(SDNode *Node);
97 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
102 SDNode *Node, bool isSigned);
103 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
107 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
113 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
114 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results)
[all...] |
| LegalizeVectorOps.cpp | 94 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
144 SDNode* Node = Op.getNode();
182 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.h | 162 virtual void ReplaceNodeResults(SDNode *N,
|
| NVPTXISelLowering.cpp | 652 // INLINEASM SDNode.
797 SDNode *Node = Op.getNode();
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetInstrInfo.cpp | 575 SDNode *DefNode, unsigned DefIdx,
576 SDNode *UseNode, unsigned UseIdx) const {
591 SDNode *N) const {
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 419 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
422 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
429 SDNode *MultNode = MultHi.getNode();
492 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
495 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
502 SDNode *MultNode = MultHi.getNode();
557 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
570 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
583 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
692 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 221 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| DAGISelMatcherEmitter.cpp | 619 OS << "virtual bool CheckNodePredicate(SDNode *Node,\n";
639 OS << "virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent,\n";
641 OS << " SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {\n";
684 // FIXME: The node xform could take SDValue's instead of SDNode*'s.
689 Record *SDNode = Entry.first;
697 std::string ClassName = CGP.getSDNodeInfo(SDNode).getSDClassName();
698 if (ClassName == "SDNode")
699 OS << " SDNode *N = V.getNode();\n";
793 OS << "SDNode *SelectCode(SDNode *N) {\n"
[all...] |
