| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 45 SDValue InFlag = SDValue(Mul, 0);
50 InFlag = SDValue(Lo, 1);
113 SDValue Mips16DAGToDAGISel::getMips16SPAliasReg() {
119 void Mips16DAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) {
120 SDValue AliasFPReg = CurDAG->getRegister(Mips::S0, TLI.getPointerTy());
153 SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset,
154 SDValue &Alias)
[all...] |
| Mips16ISelLowering.h | 46 getOpndList(SmallVectorImpl<SDValue> &Ops,
47 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
49 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
|
| MipsSEISelDAGToDAG.cpp | 187 SDValue InFlag = SDValue(Mul, 0);
192 InFlag = SDValue(Lo, 1);
201 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
202 SDValue CmpLHS, DebugLoc DL,
210 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
211 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
216 SDValue(Carry, 0), RHS);
218 SDValue(AddCarry, 0));
223 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDILISelLowering.cpp | 258 const SDValue Op,
295 SDValue
296 AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
298 SDValue DST;
307 DST = SDValue(Op.getNode(), 0);
312 SDValue
313 AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const {
315 SDValue DST;
325 DST = SDValue(Op.getNode(), 0);
330 SDValue
[all...] |
| AMDILISelDAGToDAG.cpp | 50 inline SDValue getSmallIPtrImm(unsigned Imm);
51 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
54 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
55 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
56 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2)
[all...] |
| R600ISelLowering.cpp | 311 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
322 SDValue Chain = Op.getOperand(0);
335 const SDValue Args[8] = {
377 DL, MVT::f32, SDValue(interp, 0));
395 return SDValue(interp, slot % 2);
440 return SDValue();
444 SmallVectorImpl<SDValue> &Results,
451 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
452 Results.push_back(SDValue(Node, 0))
[all...] |
| SIISelLowering.cpp | 80 SDValue SITargetLowering::LowerFormalArguments(
81 SDValue Chain,
86 SmallVectorImpl<SDValue> &InVals) const {
155 InVals.push_back(SDValue());
177 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
186 SmallVector<SDValue, 4> Regs;
245 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
251 return SDValue();
255 static SDNode *findUser(SDValue Value, unsigned Opcode)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 42 SDValue Reg;
106 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
107 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
108 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
111 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
112 std::vector<SDValue> &OutOps);
120 SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
123 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp)
[all...] |
| MSP430ISelLowering.cpp | 186 SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
251 SDValue
252 MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
259 SmallVectorImpl<SDValue> &InVals)
275 SDValue
277 SmallVectorImpl<SDValue> &InVals) const {
281 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
283 SDValue Chain = CLI.Chain;
284 SDValue Callee = CLI.Callee
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypesGeneric.cpp | 34 SDValue &Lo, SDValue &Hi) {
35 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
39 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
42 SDValue InOp = N->getOperand(0);
113 SDValue CastInOp = DAG.getNode(ISD::BITCAST, dl, NVT, InOp);
115 SmallVector<SDValue, 8> Vals;
125 SDValue LHS = Vals[Slot];
126 SDValue RHS = Vals[Slot + 1]
[all...] |
| LegalizeDAG.cpp | 72 SDValue OptimizeFloatStore(StoreSDNode *ST);
81 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
82 SDValue Idx, DebugLoc dl);
83 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
84 SDValue Idx, DebugLoc dl);
90 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl
[all...] |
| SelectionDAGBuilder.cpp | 90 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
91 const SDValue *Parts, unsigned NumParts,
99 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
100 const SDValue *Parts,
110 SDValue Val = Parts[0];
124 SDValue Lo, Hi;
166 SDValue Lo, Hi;
220 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
221 const SDValue *Parts, unsigned NumParts,
226 SDValue Val = Parts[0]
[all...] |
| SelectionDAGBuilder.h | 86 DenseMap<const Value*, SDValue> NodeMap;
90 DenseMap<const Value*, SDValue> UnusedArgNodeMap;
115 SmallVector<SDValue, 8> PendingLoads;
123 SmallVector<SDValue, 8> PendingExports;
359 SDValue getRoot();
365 SDValue getControlRoot();
384 void resolveDanglingDebugInfo(const Value *V, SDValue Val);
385 SDValue getValue(const Value *V);
386 SDValue getNonRegisterValue(const Value *V);
387 SDValue getValueImpl(const Value *V)
[all...] |
| InstrEmitter.cpp | 85 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
89 SDValue Op(Node, ResNo);
124 SDValue Op = User->getOperand(i);
180 SDValue Op(Node, ResNo);
210 DenseMap<SDValue, unsigned> &VRBaseMap) {
256 SDValue Op(Node, i);
267 unsigned InstrEmitter::getVR(SDValue Op,
268 DenseMap<SDValue, unsigned> &VRBaseMap) {
285 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
296 SDValue Op
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 824 DebugLoc DL, SDValue &Chain) const {
830 SmallVector<SDValue, 8> MemOps;
842 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
846 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
847 SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN,
861 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
59 SDValue V2);
66 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
93 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
94 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
105 static SDValue Insert128BitVector(SDValue Result, SDValue Vec
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | 84 /// SDValue - Unlike LLVM values, Selection DAG nodes may return multiple
92 /// of information is represented with the SDValue value type.
94 class SDValue {
98 SDValue() : Node(0), ResNo(0) {}
99 SDValue(SDNode *node, unsigned resno) : Node(node), ResNo(resno) {}
112 bool operator==(const SDValue &O) const {
115 bool operator!=(const SDValue &O) const {
118 bool operator<(const SDValue &O) const {
122 SDValue getValue(unsigned R) const {
123 return SDValue(Node, R)
[all...] |
| Analysis.h | 30 class SDValue;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 615 static bool isFloatingPointZero(SDValue Op) {
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 243 SDValue
244 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
410 SDValue
412 SmallVectorImpl<SDValue> &InVals) const {
416 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
418 SDValue Chain = CLI.Chain;
419 SDValue Callee = CLI.Callee;
427 SDValue tempChain = Chain;
430 SDValue InFlag = Chain.getValue(1);
450 SDValue DeclareParamOps[] = { Chain
[all...] |
| NVPTXISelDAGToDAG.cpp | 217 SDValue Chain = N->getOperand(0);
218 SDValue N1 = N->getOperand(1);
219 SDValue Addr;
220 SDValue Offset, Base;
234 SDValue Ops[] = { getI32Imm(isVolatile),
254 SDValue Ops[] = { getI32Imm(isVolatile),
286 SDValue Ops[] = { getI32Imm(isVolatile),
317 SDValue Ops[] = { getI32Imm(isVolatile),
338 SDValue Chain = N->getOperand(0);
339 SDValue Op1 = N->getOperand(1)
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 199 SDValue MBlazeTargetLowering::LowerOperation(SDValue Op,
210 return SDValue();
572 SDValue MBlazeTargetLowering::LowerSELECT_CC(SDValue Op,
574 SDValue LHS = Op.getOperand(0);
575 SDValue RHS = Op.getOperand(1);
576 SDValue TrueVal = Op.getOperand(2);
577 SDValue FalseVal = Op.getOperand(3);
581 SDValue CompareFlag
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 274 SDValue
275 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
277 return SDValue();
285 static SDValue
286 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
290 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
300 SDValue
301 HexagonTargetLowering::LowerReturn(SDValue Chain
[all...] |
