| /external/compiler-rt/lib/arm/ |
| subsf3vfp.S | 24 vsub.f32 s14, s14, s15
|
| unordsf2vfp.S | 24 vcmp.f32 s14, s15
|
| /external/llvm/test/MC/ARM/ |
| simple-fp-encoding.s | 4 vadd.f32 s0, s1, s0
6 @ CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee]
9 vsub.f32 s0, s1, s0
11 @ CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee]
14 vdiv.f32 s0, s1, s0
15 vdiv.f32 s5, s7
19 @ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee]
20 @ CHECK: vdiv.f32 s5, s5, s7 @ encoding: [0xa3,0x2a,0xc2,0xee]
26 vmul.f32 s0, s1, s0
27 vmul.f32 s11, s2
[all...] |
| neon-cmp-encoding.s | 6 vceq.f32 d16, d16, d17
10 vceq.f32 q8, q8, q9
15 @ CHECK: vceq.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf2]
19 @ CHECK: vceq.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf2]
27 vcge.f32 d16, d16, d17
34 vcge.f32 q8, q8, q9
35 vacge.f32 d16, d16, d17
36 vacge.f32 q8, q8, q9
44 @ CHECK: vcge.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf3]
51 @ CHECK: vcge.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf3
[all...] |
| neon-abs-encoding.s | 9 @ CHECK: vabs.f32 d16, d16 @ encoding: [0x20,0x07,0xf9,0xf3]
10 vabs.f32 d16, d16
17 @ CHECK: vabs.f32 q8, q8 @ encoding: [0x60,0x07,0xf9,0xf3]
18 vabs.f32 q8, q8
|
| neon-minmax-encoding.s | 9 vmax.f32 d19, d20, d21
17 vmax.f32 d20, d21
25 vmax.f32 q9, q5, q1
33 vmax.f32 q2, q1
41 @ CHECK: vmax.f32 d19, d20, d21 @ encoding: [0xa5,0x3f,0x44,0xf2]
48 @ CHECK: vmax.f32 d20, d20, d21 @ encoding: [0xa5,0x4f,0x44,0xf2]
55 @ CHECK: vmax.f32 q9, q5, q1 @ encoding: [0x42,0x2f,0x4a,0xf2]
62 @ CHECK: vmax.f32 q2, q2, q1 @ encoding: [0x42,0x4f,0x04,0xf2]
71 vmin.f32 d19, d20, d21
79 vmin.f32 d20, d2
[all...] |
| neon-neg-encoding.s | 9 @ CHECK: vneg.f32 d16, d16 @ encoding: [0xa0,0x07,0xf9,0xf3]
10 vneg.f32 d16, d16
17 @ CHECK: vneg.f32 q8, q8 @ encoding: [0xe0,0x07,0xf9,0xf3]
18 vneg.f32 q8, q8
|
| neont2-abs-encoding.s | 11 @ CHECK: vabs.f32 d16, d16 @ encoding: [0xf9,0xff,0x20,0x07]
12 vabs.f32 d16, d16
19 @ CHECK: vabs.f32 q8, q8 @ encoding: [0xf9,0xff,0x60,0x07]
20 vabs.f32 q8, q8
|
| neont2-minmax-encoding.s | 11 vmax.f32 d19, d20, d21
19 vmax.f32 d20, d21
27 vmax.f32 q9, q5, q1
35 vmax.f32 q2, q1
43 @ CHECK: vmax.f32 d19, d20, d21 @ encoding: [0x44,0xef,0xa5,0x3f]
50 @ CHECK: vmax.f32 d20, d20, d21 @ encoding: [0x44,0xef,0xa5,0x4f]
57 @ CHECK: vmax.f32 q9, q5, q1 @ encoding: [0x4a,0xef,0x42,0x2f]
64 @ CHECK: vmax.f32 q2, q2, q1 @ encoding: [0x04,0xef,0x42,0x4f]
73 vmin.f32 d19, d20, d21
81 vmin.f32 d20, d2
[all...] |
| neont2-neg-encoding.s | 11 @ CHECK: vneg.f32 d16, d16 @ encoding: [0xf9,0xff,0xa0,0x07]
12 vneg.f32 d16, d16
19 @ CHECK: vneg.f32 q8, q8 @ encoding: [0xf9,0xff,0xe0,0x07]
20 vneg.f32 q8, q8
|
| neon-mul-accum-encoding.s | 6 vmla.f32 d16, d18, d17
10 vmla.f32 q9, q8, q10
16 @ CHECK: vmla.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x42,0xf2]
20 @ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x40,0xf2]
57 vmls.f32 d16, d18, d17
61 vmls.f32 q9, q8, q10
67 @ CHECK: vmls.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x62,0xf2]
71 @ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x60,0xf2]
|
| neon-mul-encoding.s | 6 vmul.f32 d16, d16, d17
10 vmul.f32 q8, q8, q9
18 vmul.f32 d16, d17
22 vmul.f32 q8, q9
29 @ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0xb1,0x0d,0x40,0xf3]
33 @ CHECK: vmul.f32 q8, q8, q9 @ encoding: [0xf2,0x0d,0x40,0xf3]
41 @ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0xb1,0x0d,0x40,0xf3]
45 @ CHECK: vmul.f32 q8, q8, q9 @ encoding: [0xf2,0x0d,0x40,0xf3]
112 vmul.f32 d6, d5[1]
120 vmul.f32 q6, d5[1
[all...] |
| neont2-pairwise-encoding.s | 7 vpadd.f32 d19, d16, d14
12 @ CHECK: vpadd.f32 d19, d16, d14 @ encoding: [0x40,0xff,0x8e,0x3d]
75 vpmin.f32 d22, d23, d16
83 @ CHECK: vpmin.f32 d22, d23, d16 @ encoding: [0x67,0xff,0xa0,0x6f]
92 vpmax.f32 d9, d26, d11
100 @ CHECK: vpmax.f32 d9, d26, d11 @ encoding: [0x0a,0xff,0x8b,0x9f]
|
| /external/qemu/target-arm/ |
| helper.h | 77 DEF_HELPER_3(vfp_adds, f32, f32, f32, env)
79 DEF_HELPER_3(vfp_subs, f32, f32, f32, env)
81 DEF_HELPER_3(vfp_muls, f32, f32, f32, env)
83 DEF_HELPER_3(vfp_divs, f32, f32, f32, env
[all...] |
| /external/valgrind/main/none/tests/arm/ |
| vfp.stdout.exp | 142 vmla.f32 s0, s11, s12 :: Sd 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x7fc00000
143 vmla.f32 s7, s1, s6 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000
144 vmla.f32 s0, s5, s2 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0xbf800000
145 vmla.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000
146 vmla.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000
147 vmla.f32 s20, s25, s22 :: Sd 0xc4833ce4 Sm (i32)0x41b851ec Sn (i32)0xc2364659
148 vmla.f32 s23, s24, s25 :: Sd 0xcddf4321 Sm (i32)0xc8a9da0f Sn (i32)0x44a84000
149 vmla.f32 s20, s31, s12 :: Sd 0xcf050e7f Sm (i32)0x473e7300 Sn (i32)0xc732da7a
150 vmla.f32 s19, s25, s27 :: Sd 0x4ec3063f Sm (i32)0x47bb3de1 Sn (i32)0x46855200
151 vmla.f32 s30, s15, s2 :: Sd 0x5029254c Sm (i32)0xc732633d Sn (i32)0xc872bcb
[all...] |
| neon128.stdout.exp | 22 vmov.f32 q0, #0.328125 :: Qd 0x3ea80000 0x3ea80000 0x3ea80000 0x3ea80000
23 vmov.f32 q0, #0.328125 :: Qd 0x3ea80000 0x3ea80000 0x3ea80000 0x3ea80000
24 vmov.f32 q0, #-0.328125 :: Qd 0xbea80000 0xbea80000 0xbea80000 0xbea80000
25 vmov.f32 q0, #-0.328125 :: Qd 0xbea80000 0xbea80000 0xbea80000 0xbea80000
[all...] |
| /external/valgrind/main/none/tests/s390x/ |
| fpconv.c | 28 float f32; \
29 printf(#insn " %f\n", I2F(insn, 0, f32, round)); \
30 printf(#insn " %f\n", I2F(insn, 1, f32, round)); \
31 printf(#insn " %f\n", I2F(insn, 0xffffffffUL, f32, round)); \
32 printf(#insn " %f\n", I2F(insn, 0x80000000UL, f32, round)); \
33 printf(#insn " %f\n", I2F(insn, 0x7fffffffUL, f32, round)); \
34 printf(#insn " %f\n", I2F(insn, 0x100000000UL, f32, round)); \
35 printf(#insn " %f\n", I2F(insn, 0xffffffffffffffffUL, f32, round)); \
36 printf(#insn " %f\n", I2F(insn, 0x8000000000000000UL, f32, round)); \
37 printf(#insn " %f\n", I2F(insn, 0x7fffffffffffffffUL, f32, round));
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 283 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
284 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 },
287 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
288 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
291 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 },
292 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 },
295 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 },
296 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 },
299 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 },
300 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 }
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 48 " IEEE Compliant F32 div.rnd if avaiable."),
64 // Always do fma.f32 fpcontract if the target supports the instruction.
66 // Do mad.f32 is nvptx-mad-enable is specified and the target does not
67 // support fma.f32.
85 // Decide how to translate f32 div
230 case MVT::f32: Opcode = NVPTX::LD_f32_avar; break;
250 case MVT::f32: Opcode = NVPTX::LD_f32_asi; break;
271 case MVT::f32: Opcode = NVPTX::LD_f32_ari_64; break;
281 case MVT::f32: Opcode = NVPTX::LD_f32_ari; break;
302 case MVT::f32: Opcode = NVPTX::LD_f32_areg_64; break
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 41 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
42 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
43 setOperationAction(ISD::FPOW, MVT::f32, Legal);
44 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
45 setOperationAction(ISD::FABS, MVT::f32, Legal);
46 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
47 setOperationAction(ISD::FRINT, MVT::f32, Legal);
51 setOperationAction(ISD::STORE, MVT::f32, Promote);
52 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
57 setOperationAction(ISD::LOAD, MVT::f32, Promote)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 116 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
155 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
230 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
247 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
856 RegVT == MVT::i32 || RegVT == MVT::f32) {
[all...] |
| /external/skia/include/views/ |
| SkEvent.h | 110 uint32_t getFast32() const { return f32; }
115 void setFast32(uint32_t x) { f32 = x; }
266 uint32_t f32; member in class:SkEvent
|
| /external/skia/legacy/include/views/ |
| SkEvent.h | 112 uint32_t getFast32() const { return f32; }
117 void setFast32(uint32_t x) { f32 = x; }
276 uint32_t f32; member in class:SkEvent
|
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 372 if (OpVT == MVT::f32) {
388 if (RetVT == MVT::f32) {
412 if (OpVT == MVT::f32) {
462 if (OpVT == MVT::f32) {
513 if (RetVT == MVT::f32)
524 if (RetVT == MVT::f32)
535 if (RetVT == MVT::f32)
553 if (RetVT == MVT::f32)
564 if (RetVT == MVT::f32)
575 if (RetVT == MVT::f32)
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 67 addRegisterClass(MVT::f32, &MBlaze::GPRRegClass);
68 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
72 setOperationAction(ISD::FREM, MVT::f32, Expand);
73 setOperationAction(ISD::FMA, MVT::f32, Expand);
78 setOperationAction(ISD::FP_ROUND, MVT::f32, Expand);
80 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
82 setOperationAction(ISD::FSIN, MVT::f32, Expand);
83 setOperationAction(ISD::FCOS, MVT::f32, Expand);
84 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
85 setOperationAction(ISD::FPOWI, MVT::f32, Expand)
[all...] |
